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| author |   Yan Zhao <yan.y.zhao@intel.com> | 2019-05-07 22:16:33 -0400 |
|---|---|---|
| committer |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2019-05-21 10:57:57 +0800 |
| commit | b6241002039118d6bea78f50f8f19195b41ab602 (patch) | |
| tree | f9fabab5ce03fa1f35e84aafaf652553ab695f87 /drivers/gpu | |
| parent | drm/i915/gvt: Tiled Resources mmios are in-context mmios for gen9+ (diff) | |
| download | linux-dev-b6241002039118d6bea78f50f8f19195b41ab602.tar.xz linux-dev-b6241002039118d6bea78f50f8f19195b41ab602.zip | |
drm/i915/gvt: add 0x4dfc to gen9 save-restore list
0x4dfc is in-context mmio for gen9+, but each vm have different settings
need to add it to save-restore list along with other trtt registers
Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/mmio_context.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index f4e60d736cfb..90bb3df0db50 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -114,6 +114,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */ {RCS0, TRVADR, 0, true}, /* 0x4df0 */ {RCS0, TRTTE, 0, true}, /* 0x4df4 */ + {RCS0, _MMIO(0x4dfc), 0, true}, {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ |