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| author |   Mario Limonciello <mario.limonciello@amd.com> | 2021-11-04 10:44:50 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-11-05 14:11:43 -0400 |
| commit | c451c979eafc3b7ffc1527c724058245ae41b01e (patch) | |
| tree | 1daad9c8cf5593edfe795aa7b7422679976127d6 /drivers/gpu | |
| parent | drm/amd/amdgpu: Fix csb.bo pin_count leak on gfx 9 (diff) | |
| download | linux-dev-c451c979eafc3b7ffc1527c724058245ae41b01e.tar.xz linux-dev-c451c979eafc3b7ffc1527c724058245ae41b01e.zip | |
drm/amd/pm: Correct DPMS disable IP version check
Previously there was a check based on chip # for chips that aligned to
>=CHIP_NAVI10 to have RLC stopped as part of DPMS check. This was because
of gfxclk being controlled by RLC in the newer designs.
As part of IP version checking though, this got changed to match IP
version for SMU. Because Renoir designs also include smu11 that meant
that even GFX9 started to stop RLC earlier.
Adjust to match GFX IP version instead of SMU IP version to restore the
previous behavior.
Fixes: a8967967f6a5 ("drm/amdgpu/amdgpu_smu: convert to IP version checking")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 821ae6e78703..01168b8955bf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1468,7 +1468,7 @@ static int smu_disable_dpms(struct smu_context *smu) dev_err(adev->dev, "Failed to disable smu features.\n"); } - if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0) && + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0) && adev->gfx.rlc.funcs->stop) adev->gfx.rlc.funcs->stop(adev); |