diff options
| author |   James Clark <james.clark@arm.com> | 2022-03-04 17:19:07 +0000 |
|---|---|---|
| committer |   Mathieu Poirier <mathieu.poirier@linaro.org> | 2022-04-13 11:05:17 -0600 |
| commit | 4bc500ef252e44fd95c0402fb0b2c714a5bf94b8 (patch) | |
| tree | 284c339c1a4b72c4559706773134536b32676c0b /drivers/hwtracing/coresight/coresight-etm3x-core.c | |
| parent | coresight: etm4x: Cleanup TRCVICTLR register accesses (diff) | |
| download | linux-dev-4bc500ef252e44fd95c0402fb0b2c714a5bf94b8.tar.xz linux-dev-4bc500ef252e44fd95c0402fb0b2c714a5bf94b8.zip | |
coresight: etm3x: Cleanup ETMTECR1 register accesses
This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. These fields already have macros
to define them so use them instead of magic numbers.
Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-11-james.clark@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-etm3x-core.c')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 7d413ba8b823..d0ab9933472b 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -204,7 +204,7 @@ void etm_set_default(struct etm_config *config) * set all bits in register 0x007, the ETMTECR2, to 0 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). */ - config->enable_ctrl1 = BIT(24); + config->enable_ctrl1 = ETMTECR1_INC_EXC; config->enable_ctrl2 = 0x0; config->enable_event = ETM_HARD_WIRE_RES_A; |