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| author |   James Clark <james.clark@arm.com> | 2022-03-04 17:19:03 +0000 |
|---|---|---|
| committer |   Mathieu Poirier <mathieu.poirier@linaro.org> | 2022-04-13 11:04:50 -0600 |
| commit | 1cf50f6494644ffb67cafa8f5141cbeaf21a5102 (patch) | |
| tree | 0340268b90e63da85e7275f63194e5a2068c7cd5 /drivers/hwtracing/coresight/coresight-etm4x.h | |
| parent | coresight: etm4x: Cleanup TRCIDR5 register accesses (diff) | |
| download | linux-dev-1cf50f6494644ffb67cafa8f5141cbeaf21a5102.tar.xz linux-dev-1cf50f6494644ffb67cafa8f5141cbeaf21a5102.zip | |
coresight: etm4x: Cleanup TRCCONFIGR register accesses
This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.
Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-7-james.clark@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-etm4x.h')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-etm4x.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 3b604cde668b..4c8d7be3c159 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -172,6 +172,22 @@ #define TRCIDR5_NUMSEQSTATE_MASK GENMASK(27, 25) #define TRCIDR5_NUMCNTR_MASK GENMASK(30, 28) +#define TRCCONFIGR_INSTP0_LOAD BIT(1) +#define TRCCONFIGR_INSTP0_STORE BIT(2) +#define TRCCONFIGR_INSTP0_LOAD_STORE (TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE) +#define TRCCONFIGR_BB BIT(3) +#define TRCCONFIGR_CCI BIT(4) +#define TRCCONFIGR_CID BIT(6) +#define TRCCONFIGR_VMID BIT(7) +#define TRCCONFIGR_COND_MASK GENMASK(10, 8) +#define TRCCONFIGR_TS BIT(11) +#define TRCCONFIGR_RS BIT(12) +#define TRCCONFIGR_QE_W_COUNTS BIT(13) +#define TRCCONFIGR_QE_WO_COUNTS BIT(14) +#define TRCCONFIGR_VMIDOPT BIT(15) +#define TRCCONFIGR_DA BIT(16) +#define TRCCONFIGR_DV BIT(17) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions |