diff options
| author |   James Clark <james.clark@arm.com> | 2022-03-04 17:19:06 +0000 |
|---|---|---|
| committer |   Mathieu Poirier <mathieu.poirier@linaro.org> | 2022-04-13 11:05:10 -0600 |
| commit | 6ba7f2bc12e8a913f6164a4caf6ce7b93e991e32 (patch) | |
| tree | abdf055835020ec61250655ff1739c9490ee3b24 /drivers/hwtracing/coresight/coresight-etm4x.h | |
| parent | coresight: etm4x: Cleanup TRCSTALLCTLR register accesses (diff) | |
| download | linux-dev-6ba7f2bc12e8a913f6164a4caf6ce7b93e991e32.tar.xz linux-dev-6ba7f2bc12e8a913f6164a4caf6ce7b93e991e32.zip | |
coresight: etm4x: Cleanup TRCVICTLR register accesses
This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.
Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-10-james.clark@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-etm4x.h')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-etm4x.h | 22 |
1 files changed, 8 insertions, 14 deletions
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 36934056a5dc..9cacc38b1890 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -200,6 +200,14 @@ #define TRCSTALLCTLR_INSTPRIORITY BIT(10) #define TRCSTALLCTLR_NOOVERFLOW BIT(13) +#define TRCVICTLR_EVENT_MASK GENMASK(7, 0) +#define TRCVICTLR_SSSTATUS BIT(9) +#define TRCVICTLR_TRCRESET BIT(10) +#define TRCVICTLR_TRCERR BIT(11) +#define TRCVICTLR_EXLEVEL_MASK GENMASK(22, 16) +#define TRCVICTLR_EXLEVEL_S_MASK GENMASK(19, 16) +#define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(22, 20) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions @@ -700,23 +708,9 @@ #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ -#define ETM_EXLEVEL_MASK (GENMASK(6, 0)) -#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) -#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) - /* access level controls in TRCACATRn */ #define TRCACATR_EXLEVEL_SHIFT 8 -/* access level control in TRCVICTLR */ -#define TRCVICTLR_EXLEVEL_SHIFT 16 -#define TRCVICTLR_EXLEVEL_S_SHIFT 16 -#define TRCVICTLR_EXLEVEL_NS_SHIFT 20 - -/* secure / non secure masks - TRCVICTLR, IDR3 */ -#define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT) -#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) -#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) - #define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 #define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) #define ETM_TRCIDR1_ARCH_MAJOR(x) \ |