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authorJames Clark <james.clark@arm.com>2022-08-30 18:26:13 +0100
committerMathieu Poirier <mathieu.poirier@linaro.org>2022-08-31 10:56:36 -0600
commit0a98181f805058773961c5ab3172ecf1bf1ed0e1 (patch)
tree2d3fe2b4f9573852c01633b0666085bdae072ac5 /drivers/hwtracing/coresight/coresight-priv.h
parentcoresight: cti-sysfs: Re-use same functions for similar sysfs register accessors (diff)
downloadlinux-dev-0a98181f805058773961c5ab3172ecf1bf1ed0e1.tar.xz
linux-dev-0a98181f805058773961c5ab3172ecf1bf1ed0e1.zip
coresight: Make new csdev_access offsets unsigned
New csdev_access functions were added as part of the previous refactor. In order to make them more consistent with the existing ones, change any signed offset types to be unsigned. Now that they are unsigned, stop using hi_off = -1 to signify a single 32bit access. Instead just call the existing 32bit accessors. This is also applied to other parts of the codebase, and the coresight_{read,write}_reg_pair() functions can be deleted. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220830172614.340962-6-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-priv.h')
-rw-r--r--drivers/hwtracing/coresight/coresight-priv.h35
1 files changed, 9 insertions, 26 deletions
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index c211979deca5..595ce5862056 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -41,8 +41,8 @@
#define ETM_MODE_EXCL_USER BIT(31)
struct cs_pair_attribute {
struct device_attribute attr;
- s32 lo_off;
- s32 hi_off;
+ u32 lo_off;
+ u32 hi_off;
};
struct cs_off_attribute {
@@ -50,21 +50,23 @@ struct cs_off_attribute {
u32 off;
};
-extern ssize_t coresight_simple_show(struct device *_dev,
+extern ssize_t coresight_simple_show32(struct device *_dev,
+ struct device_attribute *attr, char *buf);
+extern ssize_t coresight_simple_show_pair(struct device *_dev,
struct device_attribute *attr, char *buf);
#define coresight_simple_reg32(name, offset) \
- (&((struct cs_pair_attribute[]) { \
+ (&((struct cs_off_attribute[]) { \
{ \
- __ATTR(name, 0444, coresight_simple_show, NULL), \
- offset, -1 \
+ __ATTR(name, 0444, coresight_simple_show32, NULL), \
+ offset \
} \
})[0].attr.attr)
#define coresight_simple_reg64(name, lo_off, hi_off) \
(&((struct cs_pair_attribute[]) { \
{ \
- __ATTR(name, 0444, coresight_simple_show, NULL), \
+ __ATTR(name, 0444, coresight_simple_show_pair, NULL), \
lo_off, hi_off \
} \
})[0].attr.attr)
@@ -130,25 +132,6 @@ static inline void CS_UNLOCK(void __iomem *addr)
} while (0);
}
-static inline u64
-coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
-{
- u64 val;
-
- val = readl_relaxed(addr + lo_offset);
- val |= (hi_offset < 0) ? 0 :
- (u64)readl_relaxed(addr + hi_offset) << 32;
- return val;
-}
-
-static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
- s32 lo_offset, s32 hi_offset)
-{
- writel_relaxed((u32)val, addr + lo_offset);
- if (hi_offset >= 0)
- writel_relaxed((u32)(val >> 32), addr + hi_offset);
-}
-
void coresight_disable_path(struct list_head *path);
int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data);
struct coresight_device *coresight_get_sink(struct list_head *path);