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| author |   Tamal Saha <tamal.saha@intel.com> | 2021-12-15 17:12:00 +0200 |
|---|---|---|
| committer |   Wolfram Sang <wsa@kernel.org> | 2021-12-16 22:13:24 +0100 |
| commit | f4e0ba52a89fc2f1b009b3f6af8e617ad1a3c315 (patch) | |
| tree | 06715956bfeb78238aa15b1d6012053af2dc9b7d /drivers/i2c | |
| parent | i2c: tegra: use i2c_timings for bus clock freq (diff) | |
| download | linux-dev-f4e0ba52a89fc2f1b009b3f6af8e617ad1a3c315.tar.xz linux-dev-f4e0ba52a89fc2f1b009b3f6af8e617ad1a3c315.zip | |
i2c: designware: Do not complete i2c read without RX_FULL interrupt
Intel Keem Bay platform supports multi-master operations over same i2c
bus using Synopsys i2c DesignWare IP. When multi-masters initiate i2c
operation simultaneously in a loop, SCL line is stucked low forever
after few i2c operations. Following interrupt sequences are observed
in:
working case: TX_EMPTY, RX_FULL and STOP_DET
non working case: TX_EMPTY, STOP_DET, RX_FULL.
DW_apb_i2c stretches the SCL line when the TX FIFO is empty or when
RX FIFO is full. The DW_apb_i2c master will continue to hold the SCL
line LOW until RX FIFO is read.
Linux kernel i2c DesignWare driver does not handle above non working
sequence. TX_EMPTY, RX_FULL and STOP_DET routine execution are required
in sequence although RX_FULL interrupt is raised after STOP_DET by
hardware. Clear STOP_DET for the following conditions:
(STOP_DET ,RX_FULL, rx_outstanding)
Write Operation: (1, 0, 0)
Read Operation:
RX_FULL followed by STOP_DET: (0, 1, 1) -> (1, 0, 0)
STOP_DET followed by RX_FULL: (1, 0, 1) -> (1, 1, 0)
RX_FULL and STOP_DET together: (1, 1, 1)
Signed-off-by: Tamal Saha <tamal.saha@intel.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/busses/i2c-designware-master.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c index 9b08bb5df38d..9177463c2cbb 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -701,7 +701,8 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); if (stat & DW_IC_INTR_ACTIVITY) regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); - if (stat & DW_IC_INTR_STOP_DET) + if ((stat & DW_IC_INTR_STOP_DET) && + ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL))) regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); if (stat & DW_IC_INTR_START_DET) regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); @@ -723,6 +724,7 @@ static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev) if (stat & DW_IC_INTR_TX_ABRT) { dev->cmd_err |= DW_IC_ERR_TX_ABRT; dev->status = STATUS_IDLE; + dev->rx_outstanding = 0; /* * Anytime TX_ABRT is set, the contents of the tx/rx @@ -745,7 +747,8 @@ static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev) */ tx_aborted: - if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) + if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) && + (dev->rx_outstanding == 0)) complete(&dev->cmd_complete); else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { /* Workaround to trigger pending interrupt */ |