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| author |   Len Brown <len.brown@intel.com> | 2010-10-23 02:33:50 -0400 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2010-10-23 02:35:23 -0400 |
| commit | 00527cc6bbcac05ab7d54c40bda1ff2a0625ab10 (patch) | |
| tree | f74a89bc9c32fb1a978e427ab6687f4231111ba0 /drivers/idle | |
| parent | acpi_idle: delete bogus data from cpuidle_state.power_usage (diff) | |
| parent | intel_idle: add initial Sandy Bridge support (diff) | |
| download | linux-dev-00527cc6bbcac05ab7d54c40bda1ff2a0625ab10.tar.xz linux-dev-00527cc6bbcac05ab7d54c40bda1ff2a0625ab10.zip | |
Merge branch 'intel_idle+snb' into idle-release
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'drivers/idle')
| -rw-r--r-- | drivers/idle/intel_idle.c | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 8e35c89d0927..d310590598f9 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -81,7 +81,7 @@ static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1; static unsigned int mwait_substates; /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ -static unsigned int lapic_timer_reliable_states; +static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state); @@ -121,6 +121,42 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = { .enter = &intel_idle }, }; +static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = { + { /* MWAIT C0 */ }, + { /* MWAIT C1 */ + .name = "SNB-C1", + .desc = "MWAIT 0x00", + .driver_data = (void *) 0x00, + .flags = CPUIDLE_FLAG_TIME_VALID, + .exit_latency = 1, + .target_residency = 4, + .enter = &intel_idle }, + { /* MWAIT C2 */ + .name = "SNB-C3", + .desc = "MWAIT 0x10", + .driver_data = (void *) 0x10, + .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 80, + .target_residency = 160, + .enter = &intel_idle }, + { /* MWAIT C3 */ + .name = "SNB-C6", + .desc = "MWAIT 0x20", + .driver_data = (void *) 0x20, + .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 104, + .target_residency = 208, + .enter = &intel_idle }, + { /* MWAIT C4 */ + .name = "SNB-C7", + .desc = "MWAIT 0x30", + .driver_data = (void *) 0x30, + .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 109, + .target_residency = 300, + .enter = &intel_idle }, +}; + static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { { /* MWAIT C0 */ }, { /* MWAIT C1 */ @@ -269,6 +305,11 @@ static int intel_idle_probe(void) lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */ cpuidle_state_table = atom_cstates; break; + + case 0x2A: /* SNB */ + case 0x2D: /* SNB Xeon */ + cpuidle_state_table = snb_cstates; + break; #ifdef FUTURE_USE case 0x17: /* 23 - Core 2 Duo */ lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */ |