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| author |   Vipul Pandya <vipul@chelsio.com> | 2013-03-14 05:09:01 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2013-03-14 11:35:59 -0400 |
| commit | 42b6a949903d28f59c95f4c71080aa8b41e3d1d1 (patch) | |
| tree | d91e9304efb9504fb03256bb5e0fb78f76da7c3d /drivers/infiniband/hw/cxgb4/t4.h | |
| parent | RDMA/cxgb4: Add module_params to enable DB FC & Coalescing on T5 (diff) | |
| download | linux-dev-42b6a949903d28f59c95f4c71080aa8b41e3d1d1.tar.xz linux-dev-42b6a949903d28f59c95f4c71080aa8b41e3d1d1.zip | |
RDMA/cxgb4: Use DSGLs for fastreg and adapter memory writes for T5.
It enables direct DMA by HW to memory region PBL arrays and fast register PBL
arrays from host memory, vs the T4 way of passing these arrays in the WR itself.
The result is lower latency for memory registration, and larger PBL array
support for fast register operations.
This patch also updates ULP_TX_MEM_WRITE command fields for T5. Ordering bit of
ULP_TX_MEM_WRITE is at bit position 22 in T5 and at 23 in T4.
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/infiniband/hw/cxgb4/t4.h')
| -rw-r--r-- | drivers/infiniband/hw/cxgb4/t4.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/cxgb4/t4.h b/drivers/infiniband/hw/cxgb4/t4.h index 689edc96155d..ebcb03bd1b72 100644 --- a/drivers/infiniband/hw/cxgb4/t4.h +++ b/drivers/infiniband/hw/cxgb4/t4.h @@ -84,7 +84,7 @@ struct t4_status_page { sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ sizeof(struct fw_ri_immd)) & ~31UL) -#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) +#define T4_MAX_FR_DEPTH (1024 / sizeof(u64)) #define T4_RQ_NUM_SLOTS 2 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) |