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| author |   Lang Cheng <chenglang@huawei.com> | 2020-11-26 15:04:10 +0800 |
|---|---|---|
| committer |   Jason Gunthorpe <jgg@nvidia.com> | 2020-11-27 12:53:59 -0400 |
| commit | bfefae9f108dfa62eb9c16c9e97086fddb4ece04 (patch) | |
| tree | e49ddb7f3444dff50e584912fec8bf024174506f /drivers/infiniband/hw/hns/hns_roce_common.h | |
| parent | RDMA/hns: Create QP with selected QPN for bank load balance (diff) | |
| download | linux-dev-bfefae9f108dfa62eb9c16c9e97086fddb4ece04.tar.xz linux-dev-bfefae9f108dfa62eb9c16c9e97086fddb4ece04.zip | |
RDMA/hns: Add support for CQ stash
Stash is a mechanism that uses the core information carried by the ARM AXI
bus to access the L3 cache. It can be used to improve the performance by
increasing the hit ratio of L3 cache. CQs need to enable stash by default.
Link: https://lore.kernel.org/r/1606374251-21512-2-git-send-email-liweihang@huawei.com
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/infiniband/hw/hns/hns_roce_common.h')
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_common.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h index f5669ff8cfeb..29469e15dfd3 100644 --- a/drivers/infiniband/hw/hns/hns_roce_common.h +++ b/drivers/infiniband/hw/hns/hns_roce_common.h @@ -53,6 +53,18 @@ #define roce_set_bit(origin, shift, val) \ roce_set_field((origin), (1ul << (shift)), (shift), (val)) +#define FIELD_LOC(field_type, field_h, field_l) field_type, field_h, field_l + +#define _hr_reg_enable(ptr, field_type, field_h, field_l) \ + ({ \ + const field_type *_ptr = ptr; \ + *((__le32 *)_ptr + (field_h) / 32) |= \ + cpu_to_le32(BIT((field_l) % 32)) + \ + BUILD_BUG_ON_ZERO((field_h) != (field_l)); \ + }) + +#define hr_reg_enable(ptr, field) _hr_reg_enable(ptr, field) + #define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3 #define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4 |