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authorYixing Liu <liuyixing1@huawei.com>2021-08-21 17:53:26 +0800
committerJason Gunthorpe <jgg@nvidia.com>2021-08-23 13:45:12 -0300
commit260f64a40198309008026447f7fda277a73ed8c3 (patch)
tree07ffa5a8eab257a2410db91cd6bd8259ac57885d /drivers/infiniband/hw
parentRDMA/hns: Remove unsupport cmdq mode (diff)
downloadlinux-dev-260f64a40198309008026447f7fda277a73ed8c3.tar.xz
linux-dev-260f64a40198309008026447f7fda277a73ed8c3.zip
RDMA/hns: Enable stash feature of HIP09
The stash feature is enabled by default on HIP09. Fixes: f93c39bc9547 ("RDMA/hns: Add support for QP stash") Fixes: bfefae9f108d ("RDMA/hns: Add support for CQ stash") Link: https://lore.kernel.org/r/1629539607-33217-3-git-send-email-liangwenpeng@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/infiniband/hw')
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_hw_v2.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index a1fb903a948d..5d594c05fc0f 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -1997,6 +1997,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
+ caps->flags |= HNS_ROCE_CAP_FLAG_STASH;
caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE;
} else {
caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;