diff options
| author |   Sohil Mehta <sohil.mehta@intel.com> | 2017-12-20 11:59:25 -0800 |
|---|---|---|
| committer |   Joerg Roedel <jroedel@suse.de> | 2018-01-17 15:02:50 +0100 |
| commit | 59103caa6839592788e7ad58b35863aac034631a (patch) | |
| tree | b645989c4381eb78047b628f04be37a602c08538 /drivers/iommu | |
| parent | iommu/vt-d: Enable upto 57 bits of domain address width (diff) | |
| download | linux-dev-59103caa6839592788e7ad58b35863aac034631a.tar.xz linux-dev-59103caa6839592788e7ad58b35863aac034631a.zip | |
iommu/vt-d: Add a check for 1GB page support
Add a check to verify IOMMU 1GB page support. If the CPU supports 1GB
pages but the IOMMU does not support it then disable SVM by not
allocating PASID tables.
Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/intel-svm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index 6643277e321e..e9a56ad09a76 100644 --- a/drivers/iommu/intel-svm.c +++ b/drivers/iommu/intel-svm.c @@ -41,6 +41,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) struct page *pages; int order; + if (cpu_feature_enabled(X86_FEATURE_GBPAGES) && + !cap_fl1gp_support(iommu->cap)) + return -EINVAL; + /* Start at 2 because it's defined as 2^(1+PSS) */ iommu->pasid_max = 2 << ecap_pss(iommu->ecap); |