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| author |   Zhen Lei <thunder.leizhen@huawei.com> | 2015-06-26 09:32:59 +0100 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2015-07-08 17:24:39 +0100 |
| commit | 5d58c6207c300340151931ad9c2cdea2d1685dc4 (patch) | |
| tree | 7689601af671e3aa4a4bab385028e736b054d51d /drivers/iommu | |
| parent | iommu/arm-smmu: Fix LOG2SIZE setting for 2-level stream tables (diff) | |
| download | linux-dev-5d58c6207c300340151931ad9c2cdea2d1685dc4.tar.xz linux-dev-5d58c6207c300340151931ad9c2cdea2d1685dc4.zip | |
iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT
The arm64 CPU architecture defines TCR[8:11] as holding the inner and
outer memory attributes for TTBR0.
This patch fixes the ARM SMMUv3 driver to pack these bits into the
context descriptor, rather than picking up the TTBR1 attributes as it
currently does.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/arm-smmu-v3.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 6b1ae4e09616..98e987a3ed3a 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -269,10 +269,10 @@ #define ARM64_TCR_TG0_SHIFT 14 #define ARM64_TCR_TG0_MASK 0x3UL #define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8 -#define ARM64_TCR_IRGN0_SHIFT 24 +#define ARM64_TCR_IRGN0_SHIFT 8 #define ARM64_TCR_IRGN0_MASK 0x3UL #define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10 -#define ARM64_TCR_ORGN0_SHIFT 26 +#define ARM64_TCR_ORGN0_SHIFT 10 #define ARM64_TCR_ORGN0_MASK 0x3UL #define CTXDESC_CD_0_TCR_SH0_SHIFT 12 #define ARM64_TCR_SH0_SHIFT 12 |