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authorLu Baolu <baolu.lu@linux.intel.com>2022-09-26 21:15:29 +0800
committerJoerg Roedel <jroedel@suse.de>2022-09-26 15:52:26 +0200
commit6ad931a232e71620c6dbb8d573ccef51f84f2566 (patch)
tree12f9b04423e9fbddaf98c49f8b15e6c3fd0910a0 /drivers/iommu
parentiommu/vt-d: Avoid unnecessary global IRTE cache invalidation (diff)
downloadlinux-dev-6ad931a232e71620c6dbb8d573ccef51f84f2566.tar.xz
linux-dev-6ad931a232e71620c6dbb8d573ccef51f84f2566.zip
iommu/vt-d: Avoid unnecessary global DMA cache invalidation
Some VT-d hardware implementations invalidate all DMA remapping hardware translation caches as part of SRTP flow. The VT-d spec adds a ESRTPS (Enhanced Set Root Table Pointer Support, section 11.4.2 in VT-d spec) capability bit to indicate this. With this bit set, software has no need to issue the global invalidation request. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Link: https://lore.kernel.org/r/20220919062523.3438951-3-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/intel/iommu.c7
-rw-r--r--drivers/iommu/intel/iommu.h1
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 7410d6232cbb..2d142ee7bbfa 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -1239,6 +1239,13 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
+ /*
+ * Hardware invalidates all DMA remapping hardware translation
+ * caches as part of SRTP flow.
+ */
+ if (cap_esrtps(iommu->cap))
+ return;
+
iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
if (sm_supported(iommu))
qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0);
diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h
index bddf6c69587d..92023dff9513 100644
--- a/drivers/iommu/intel/iommu.h
+++ b/drivers/iommu/intel/iommu.h
@@ -146,6 +146,7 @@
/*
* Decoding Capability Register
*/
+#define cap_esrtps(c) (((c) >> 63) & 1)
#define cap_esirtps(c) (((c) >> 62) & 1)
#define cap_fl5lp_support(c) (((c) >> 60) & 1)
#define cap_pi_support(c) (((c) >> 59) & 1)