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| author |   Marc Zyngier <maz@kernel.org> | 2019-07-16 14:35:17 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2019-08-20 10:04:09 +0100 |
| commit | 13d22e2e1f35f2d3cc7ddc002c23e733c2782dd4 (patch) | |
| tree | 1a3cc19743ec04936f504bd57c848432bfc3f8ef /drivers/irqchip/irq-hip04.c | |
| parent | irqdomain/debugfs: Use PAs to generate fwnode names (diff) | |
| download | linux-dev-13d22e2e1f35f2d3cc7ddc002c23e733c2782dd4.tar.xz linux-dev-13d22e2e1f35f2d3cc7ddc002c23e733c2782dd4.zip | |
irqchip/gic: Rework gic_configure_irq to take the full ICFGR base
gic_configure_irq is currently passed the (re)distributor address,
to which it applies an a fixed offset to get to the configuration
registers. This offset is constant across all GICs, or rather it was
until to v3.1...
An easy way out is for the individual drivers to pass the base
address of the configuration register for the considered interrupt.
At the same time, move part of the error handling back to the
individual drivers, as things are about to change on that front.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'drivers/irqchip/irq-hip04.c')
| -rw-r--r-- | drivers/irqchip/irq-hip04.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-hip04.c b/drivers/irqchip/irq-hip04.c index cf705827599c..1626131834a6 100644 --- a/drivers/irqchip/irq-hip04.c +++ b/drivers/irqchip/irq-hip04.c @@ -130,7 +130,12 @@ static int hip04_irq_set_type(struct irq_data *d, unsigned int type) raw_spin_lock(&irq_controller_lock); - ret = gic_configure_irq(irq, type, base, NULL); + ret = gic_configure_irq(irq, type, base + GIC_DIST_CONFIG, NULL); + if (ret && irq < 32) { + /* Misconfigured PPIs are usually not fatal */ + pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16); + ret = 0; + } raw_spin_unlock(&irq_controller_lock); |