diff options
| author |   Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2013-11-09 13:18:01 +0100 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2013-11-24 15:55:17 +0900 |
| commit | e55bc55867585e6628359fd5496316576fe58a2f (patch) | |
| tree | 6c249dc0d5d20121ec3219dbcd74eee438dd5155 /drivers/irqchip/irq-renesas-intc-irqpin.c | |
| parent | ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB (diff) | |
| download | linux-dev-e55bc55867585e6628359fd5496316576fe58a2f.tar.xz linux-dev-e55bc55867585e6628359fd5496316576fe58a2f.zip | |
irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
The SENSE register bitfield position is incorrectly computed for SoCs
that use 2-bit IRQ sense fields. Fix it.
This has been tested on the Marzen (H1) and Bockw (M1) boards.
This bug has been present since the renesas-intc-irqpin driver was
introduced by 443580486e3b9657 ("irqchip: Renesas INTC External IRQ pin
driver") in v3.10-rc1.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/irqchip/irq-renesas-intc-irqpin.c')
| -rw-r--r-- | drivers/irqchip/irq-renesas-intc-irqpin.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 82cec63a9011..3ee78f02e5d7 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, int irq, int do_mask) { - int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ - int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ + /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */ + int bitfield_width = 4; + int shift = 32 - (irq + 1) * bitfield_width; intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, shift, bitfield_width, @@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) { + /* The SENSE register is assumed to be 32-bit. */ int bitfield_width = p->config.sense_bitfield_width; - int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ + int shift = 32 - (irq + 1) * bitfield_width; dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); |