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| author |   Yongqiang Niu <yongqiang.niu@mediatek.com> | 2021-08-02 15:46:05 +0800 |
|---|---|---|
| committer |   Jassi Brar <jaswinder.singh@linaro.org> | 2021-08-30 00:20:36 -0500 |
| commit | 84fd4201b78b96f8d31f6a2624be27ad6306a9bc (patch) | |
| tree | f80d4e20872c910a10eff530c5b07ef2257e0055 /drivers/mailbox | |
| parent | dt-binding: gce: add gce header file for mt8192 (diff) | |
| download | linux-dev-84fd4201b78b96f8d31f6a2624be27ad6306a9bc.tar.xz linux-dev-84fd4201b78b96f8d31f6a2624be27ad6306a9bc.zip | |
mailbox: cmdq: add mt8192 support
add mt8192 support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'drivers/mailbox')
| -rw-r--r-- | drivers/mailbox/mtk-cmdq-mailbox.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 67a42b514429..8d39b988df9e 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -36,6 +36,8 @@ #define CMDQ_THR_WAIT_TOKEN 0x30 #define CMDQ_THR_PRIORITY 0x40 +#define GCE_GCTL_VALUE 0x48 + #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 #define CMDQ_THR_DISABLED 0x0 @@ -76,11 +78,13 @@ struct cmdq { struct clk *clock; bool suspended; u8 shift_pa; + bool control_by_sw; }; struct gce_plat { u32 thread_nr; u8 shift; + bool control_by_sw; }; u8 cmdq_get_shift_pa(struct mbox_chan *chan) @@ -121,6 +125,8 @@ static void cmdq_init(struct cmdq *cmdq) int i; WARN_ON(clk_enable(cmdq->clock) < 0); + if (cmdq->control_by_sw) + writel(0x7, cmdq->base + GCE_GCTL_VALUE); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i = 0; i <= CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); @@ -540,6 +546,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr = plat_data->thread_nr; cmdq->shift_pa = plat_data->shift; + cmdq->control_by_sw = plat_data->control_by_sw; cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, "mtk_cmdq", cmdq); @@ -605,11 +612,14 @@ static const struct dev_pm_ops cmdq_pm_ops = { static const struct gce_plat gce_plat_v2 = {.thread_nr = 16}; static const struct gce_plat gce_plat_v3 = {.thread_nr = 24}; static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3}; +static const struct gce_plat gce_plat_v5 = {.thread_nr = 24, .shift = 3, + .control_by_sw = true}; static const struct of_device_id cmdq_of_ids[] = { {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, + {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, {} }; |