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author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-01-10 18:55:43 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-01-10 18:55:43 -0800 |
commit | 9bcbf894b6872216ef61faf17248ec234e3db6bc (patch) | |
tree | b1a8fd7c99a3913a9a4ef4019ca879455e22f9e9 /drivers/media/platform/stm32/dma2d/dma2d-hw.c | |
parent | Revert "drm/amd/display: Fix for otg synchronization logic" (diff) | |
parent | media: ipu3-cio2: Add support for instantiating i2c-clients for VCMs (diff) | |
download | linux-dev-9bcbf894b6872216ef61faf17248ec234e3db6bc.tar.xz linux-dev-9bcbf894b6872216ef61faf17248ec234e3db6bc.zip |
Merge tag 'media/v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
- New sensor driver: ov5693
- A new driver for STM32 Chrom-ART Accelerator
- Added V4L2 core helper functions for VP9 codec
- Hantro driver has gained support for VP9 codecs
- Added support for Maxim MAX96712 Quad GMSL2 Deserializer
- The staging atomisp driver has gained lots of improvements, fixes and
cleanups. It now works with userptr
- Lots of random driver improvements as usual
* tag 'media/v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (397 commits)
media: ipu3-cio2: Add support for instantiating i2c-clients for VCMs
media: ipu3-cio2: Call cio2_bridge_init() before anything else
media: ipu3-cio2: Defer probing until the PMIC is fully setup
media: hantro: Add support for Allwinner H6
media: dt-bindings: allwinner: document H6 Hantro G2 binding
media: hantro: Convert imx8m_vpu_g2_irq to helper
media: hantro: move postproc enablement for old cores
media: hantro: vp9: add support for legacy register set
media: hantro: vp9: use double buffering if needed
media: hantro: add support for reset lines
media: hantro: Fix probe func error path
media: i2c: hi846: use pm_runtime_force_suspend/resume for system suspend
media: i2c: hi846: check return value of regulator_bulk_disable()
media: hi556: Support device probe in non-zero ACPI D state
media: ov5675: Support device probe in non-zero ACPI D state
media: imx208: Support device probe in non-zero ACPI D state
media: ov2740: support device probe in non-zero ACPI D state
media: ov5670: Support device probe in non-zero ACPI D state
media: ov8856: support device probe in non-zero ACPI D state
media: ov8865: Disable only enabled regulators on error path
...
Diffstat (limited to 'drivers/media/platform/stm32/dma2d/dma2d-hw.c')
-rw-r--r-- | drivers/media/platform/stm32/dma2d/dma2d-hw.c | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/drivers/media/platform/stm32/dma2d/dma2d-hw.c b/drivers/media/platform/stm32/dma2d/dma2d-hw.c new file mode 100644 index 000000000000..ea4cc84d8a39 --- /dev/null +++ b/drivers/media/platform/stm32/dma2d/dma2d-hw.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver + * + * Copyright (c) 2021 Dillon Min + * Dillon Min, <dillon.minfei@gmail.com> + * + * based on s5p-g2d + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Kamil Debski, <k.debski@samsung.com> + */ + +#include <linux/io.h> + +#include "dma2d.h" +#include "dma2d-regs.h" + +static inline u32 reg_read(void __iomem *base, u32 reg) +{ + return readl_relaxed(base + reg); +} + +static inline void reg_write(void __iomem *base, u32 reg, u32 val) +{ + writel_relaxed(val, base + reg); +} + +static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, + u32 val) +{ + reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); +} + +void dma2d_start(struct dma2d_dev *d) +{ + reg_update_bits(d->regs, DMA2D_CR_REG, CR_START, CR_START); +} + +u32 dma2d_get_int(struct dma2d_dev *d) +{ + return reg_read(d->regs, DMA2D_ISR_REG); +} + +void dma2d_clear_int(struct dma2d_dev *d) +{ + u32 isr_val = reg_read(d->regs, DMA2D_ISR_REG); + + reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f); +} + +void dma2d_config_common(struct dma2d_dev *d, enum dma2d_op_mode op_mode, + u16 width, u16 height) +{ + reg_update_bits(d->regs, DMA2D_CR_REG, CR_MODE_MASK, + op_mode << CR_MODE_SHIFT); + + reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height); +} + +void dma2d_config_out(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t o_addr) +{ + reg_update_bits(d->regs, DMA2D_CR_REG, CR_CEIE, CR_CEIE); + reg_update_bits(d->regs, DMA2D_CR_REG, CR_CTCIE, CR_CTCIE); + reg_update_bits(d->regs, DMA2D_CR_REG, CR_CAEIE, CR_CAEIE); + reg_update_bits(d->regs, DMA2D_CR_REG, CR_TCIE, CR_TCIE); + reg_update_bits(d->regs, DMA2D_CR_REG, CR_TEIE, CR_TEIE); + + if (frm->fmt->cmode >= CM_MODE_ARGB8888 && + frm->fmt->cmode <= CM_MODE_ARGB4444) + reg_update_bits(d->regs, DMA2D_OPFCCR_REG, OPFCCR_CM_MASK, + frm->fmt->cmode); + + reg_write(d->regs, DMA2D_OMAR_REG, o_addr); + + reg_write(d->regs, DMA2D_OCOLR_REG, + (frm->a_rgb[3] << 24) | + (frm->a_rgb[2] << 16) | + (frm->a_rgb[1] << 8) | + frm->a_rgb[0]); + + reg_update_bits(d->regs, DMA2D_OOR_REG, OOR_LO_MASK, + frm->line_offset & 0x3fff); +} + +void dma2d_config_fg(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t f_addr) +{ + reg_write(d->regs, DMA2D_FGMAR_REG, f_addr); + reg_update_bits(d->regs, DMA2D_FGOR_REG, FGOR_LO_MASK, + frm->line_offset); + + if (frm->fmt->cmode >= CM_MODE_ARGB8888 && + frm->fmt->cmode <= CM_MODE_A4) + reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_CM_MASK, + frm->fmt->cmode); + + reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_AM_MASK, + (frm->a_mode << 16) & 0x03); + + reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_ALPHA_MASK, + frm->a_rgb[3] << 24); + + reg_write(d->regs, DMA2D_FGCOLR_REG, + (frm->a_rgb[2] << 16) | + (frm->a_rgb[1] << 8) | + frm->a_rgb[0]); +} + +void dma2d_config_bg(struct dma2d_dev *d, struct dma2d_frame *frm, + dma_addr_t b_addr) +{ + reg_write(d->regs, DMA2D_BGMAR_REG, b_addr); + reg_update_bits(d->regs, DMA2D_BGOR_REG, BGOR_LO_MASK, + frm->line_offset); + + if (frm->fmt->cmode >= CM_MODE_ARGB8888 && + frm->fmt->cmode <= CM_MODE_A4) + reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_CM_MASK, + frm->fmt->cmode); + + reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_AM_MASK, + (frm->a_mode << 16) & 0x03); + + reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_ALPHA_MASK, + frm->a_rgb[3] << 24); + + reg_write(d->regs, DMA2D_BGCOLR_REG, + (frm->a_rgb[2] << 16) | + (frm->a_rgb[1] << 8) | + frm->a_rgb[0]); +} |