diff options
| author |   Daniel Scheller <d.scheller@gmx.net> | 2017-04-09 16:38:23 -0300 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2017-06-20 09:56:11 -0300 |
| commit | bf51bbb0448e919181294c268a15a2d119ed9a4e (patch) | |
| tree | 82548075547592430dd7d25f2df80e4473c86e20 /drivers/media | |
| parent | [media] dvb-frontends/cxd2841er: configurable IFAGCNEG (diff) | |
| download | linux-dev-bf51bbb0448e919181294c268a15a2d119ed9a4e.tar.xz linux-dev-bf51bbb0448e919181294c268a15a2d119ed9a4e.zip | |
[media] dvb-frontends/cxd2841er: more configurable TSBITS
Bits 3 and 4 of the TSCONFIG register are important for certain hardware
constellations, in that they need to be zeroed. Add a configuration flag
to toggle this.
Signed-off-by: Daniel Scheller <d.scheller@gmx.net>
Acked-by: Abylay Ospan <aospan@netup.ru>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'drivers/media')
| -rw-r--r-- | drivers/media/dvb-frontends/cxd2841er.c | 4 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/cxd2841er.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/media/dvb-frontends/cxd2841er.c b/drivers/media/dvb-frontends/cxd2841er.c index 1f577ebe25c6..d9e8be50c5fa 100644 --- a/drivers/media/dvb-frontends/cxd2841er.c +++ b/drivers/media/dvb-frontends/cxd2841er.c @@ -3794,6 +3794,10 @@ static int cxd2841er_init_tc(struct dvb_frontend *fe) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80); + /* clear TSCFG bits 3+4 */ + if (priv->flags & CXD2841ER_TSBITS) + cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18); + cxd2841er_init_stats(fe); return 0; diff --git a/drivers/media/dvb-frontends/cxd2841er.h b/drivers/media/dvb-frontends/cxd2841er.h index 4f944221c7fe..dc32f5fb6662 100644 --- a/drivers/media/dvb-frontends/cxd2841er.h +++ b/drivers/media/dvb-frontends/cxd2841er.h @@ -31,6 +31,7 @@ #define CXD2841ER_EARLY_TUNE 16 /* bit 4 */ #define CXD2841ER_NO_WAIT_LOCK 32 /* bit 5 */ #define CXD2841ER_NO_AGCNEG 64 /* bit 6 */ +#define CXD2841ER_TSBITS 128 /* bit 7 */ enum cxd2841er_xtal { SONY_XTAL_20500, /* 20.5 MHz */ |