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| author |   Dmitry Osipenko <digetx@gmail.com> | 2019-04-12 01:12:49 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-04-18 11:36:10 +0200 |
| commit | 48791f972234301a72e4c40745d0abafa0985d2d (patch) | |
| tree | 4544350565cdd6ee2159629fdf18633ac3d6f7f7 /drivers/memory/tegra | |
| parent | memory: tegra: Fix integer overflow on tick value calculation (diff) | |
| download | linux-dev-48791f972234301a72e4c40745d0abafa0985d2d.tar.xz linux-dev-48791f972234301a72e4c40745d0abafa0985d2d.zip | |
memory: tegra: Replace readl-writel with mc_readl-mc_writel
There is no need for a memory barriers on reading/writing of register
values as we only care about the read/write order, hence let's use the
common helpers.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/tegra')
| -rw-r--r-- | drivers/memory/tegra/mc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 483ac3c1a762..163b6c69e651 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -288,24 +288,24 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); do_div(tick, NSEC_PER_SEC); - value = readl(mc->regs + MC_EMEM_ARB_CFG); + value = mc_readl(mc, MC_EMEM_ARB_CFG); value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); - writel(value, mc->regs + MC_EMEM_ARB_CFG); + mc_writel(mc, value, MC_EMEM_ARB_CFG); /* write latency allowance defaults */ for (i = 0; i < mc->soc->num_clients; i++) { const struct tegra_mc_la *la = &mc->soc->clients[i].la; u32 value; - value = readl(mc->regs + la->reg); + value = mc_readl(mc, la->reg); value &= ~(la->mask << la->shift); value |= (la->def & la->mask) << la->shift; - writel(value, mc->regs + la->reg); + mc_writel(mc, value, la->reg); } /* latch new values */ - writel(MC_TIMING_UPDATE, mc->regs + MC_TIMING_CONTROL); + mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); return 0; } |