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| author |   Dmitry Osipenko <digetx@gmail.com> | 2019-04-12 01:12:47 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-04-18 11:35:38 +0200 |
| commit | 76b959a44c0b9c60cd41627cecb022c78042ad74 (patch) | |
| tree | e0c0a44de2879bbf259384f9e2dcb1986ff83201 /drivers/memory/tegra | |
| parent | memory: tegra: Properly spell "tegra" (diff) | |
| download | linux-dev-76b959a44c0b9c60cd41627cecb022c78042ad74.tar.xz linux-dev-76b959a44c0b9c60cd41627cecb022c78042ad74.zip | |
memory: tegra: Fix missed registers values latching
Some of Memory Controller registers are shadowed and require latching in
order to copy assembly state into the active, MC_EMEM_ARB_CFG is one of
these registers.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/tegra')
| -rw-r--r-- | drivers/memory/tegra/mc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a08b61a86760..1735e23dbc28 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -51,6 +51,9 @@ #define MC_EMEM_ADR_CFG 0x54 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) +#define MC_TIMING_CONTROL 0xfc +#define MC_TIMING_UPDATE BIT(0) + static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_2x_SOC { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, @@ -301,6 +304,9 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) writel(value, mc->regs + la->reg); } + /* latch new values */ + writel(MC_TIMING_UPDATE, mc->regs + MC_TIMING_CONTROL); + return 0; } |