diff options
| author |   Michel Jaouen <michel.jaouen@stericsson.com> | 2012-08-31 14:21:30 +0200 |
|---|---|---|
| committer |   Mike Turquette <mturquette@linaro.org> | 2012-09-06 17:57:21 -0700 |
| commit | 20aee5b6d7738206bfd37b352a97c75627d6fa6d (patch) | |
| tree | f45347497f0b6861521ae80246534cfce49748de /drivers/mfd/dbx500-prcmu-regs.h | |
| parent | clk: ux500: Support for prmcu_rate clock (diff) | |
| download | linux-dev-20aee5b6d7738206bfd37b352a97c75627d6fa6d.tar.xz linux-dev-20aee5b6d7738206bfd37b352a97c75627d6fa6d.zip | |
mfd: dbx500: Provide a more accurate smp_twd clock
The local timer clock is based on ARM subsystem clock. This patch
obtains a more exact value of that clock by reading PRCMU registers.
Using this increases the accuracy of the local timer events.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Rickard Andersson <rickard.andersson@stericsson.com>
Signed-off-by: Michel Jaouen <michel.jaouen@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/mfd/dbx500-prcmu-regs.h')
| -rw-r--r-- | drivers/mfd/dbx500-prcmu-regs.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h index 23108a6e3167..79c76ebdba52 100644 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ b/drivers/mfd/dbx500-prcmu-regs.h @@ -61,7 +61,8 @@ #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 #define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) -#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ 0x1 +#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) +#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) #define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 @@ -140,6 +141,7 @@ /* PRCMU clock/PLL/reset registers */ #define PRCM_PLLSOC0_FREQ (_PRCMU_BASE + 0x080) #define PRCM_PLLSOC1_FREQ (_PRCMU_BASE + 0x084) +#define PRCM_PLLARM_FREQ (_PRCMU_BASE + 0x088) #define PRCM_PLLDDR_FREQ (_PRCMU_BASE + 0x08C) #define PRCM_PLL_FREQ_D_SHIFT 0 #define PRCM_PLL_FREQ_D_MASK BITS(0, 7) |