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authorHans de Goede <hdegoede@redhat.com>2019-10-24 23:38:25 +0200
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2019-10-25 11:43:08 +0200
commited852cde25a12ea3b6fcc3afc746f773154d0bc5 (patch)
tree6f44728474e16bf0903826fb2659c807f40d8239 /drivers/mfd
parentACPI / PMIC: Do not register handlers for unhandled OpRegions (diff)
downloadlinux-dev-ed852cde25a12ea3b6fcc3afc746f773154d0bc5.tar.xz
linux-dev-ed852cde25a12ea3b6fcc3afc746f773154d0bc5.zip
ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver
Our current Crystal Cove OpRegion driver is only valid for the Crystal Cove PMIC variant found on Bay Trail (BYT) boards, Cherry Trail (CHT) based boards use another variant. At least the regulator registers are different on CHT and these registers are one of the things controlled by the custom PMIC OpRegion. Commit 4d9ed62ab142 ("mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT") has disabled the intel_pmic_crc.c code for CHT devices by removing the "crystal_cove_pmic" MFD cell on CHT devices. This commit renames the intel_pmic_crc.c driver and the cell to be prefixed with "byt" to indicate that this code is for BYT devices only. This is a preparation patch for adding a separate PMIC OpRegion driver for the CHT variant of the Crystal Cove PMIC (sometimes called Crystal Cove Plus in Android kernel sources). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/mfd')
-rw-r--r--drivers/mfd/intel_soc_pmic_crc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
index b6ab72fa0569..ab09b8225b76 100644
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -75,7 +75,7 @@ static struct mfd_cell crystal_cove_byt_dev[] = {
.resources = gpio_resources,
},
{
- .name = "crystal_cove_pmic",
+ .name = "byt_crystal_cove_pmic",
},
{
.name = "crystal_cove_pwm",