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authorIan Munsie <imunsie@au1.ibm.com>2016-05-06 17:46:36 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2016-05-11 21:54:10 +1000
commit7a0d85d313c2066712e530e668bc02bb741a685c (patch)
treeb097194d6a8a1b8144efe32dc2222558dd64626f /drivers/misc/cxl/native.c
parentcxl: Ensure PSL interrupt is configured for contexts with no AFU IRQs (diff)
downloadlinux-dev-7a0d85d313c2066712e530e668bc02bb741a685c.tar.xz
linux-dev-7a0d85d313c2066712e530e668bc02bb741a685c.zip
cxl: Add kernel API to allow a context to operate with relocate disabled
cxl devices typically access memory using an MMU in much the same way as the CPU, and each context includes a state register much like the MSR in the CPU. Like the CPU, the state register includes a bit to enable relocation, which we currently always enable. In some cases, it may be desirable to allow a device to access memory using real addresses instead of effective addresses, so this adds a new API, cxl_set_translation_mode, that can be used to disable relocation on a given kernel context. This can allow for the creation of a special privileged context that the device can use if it needs relocation disabled, and can use regular contexts at times when it needs relocation enabled. This interface is only available to users of the kernel API for obvious reasons, and will never be supported in a virtualised environment. This will be used by the upcoming cxl support in the mlx5 driver. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'drivers/misc/cxl/native.c')
-rw-r--r--drivers/misc/cxl/native.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 5d4fb9fd84bc..98f2cac45162 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/misc/cxl/native.c
@@ -494,8 +494,9 @@ static u64 calculate_sr(struct cxl_context *ctx)
if (mfspr(SPRN_LPCR) & LPCR_TC)
sr |= CXL_PSL_SR_An_TC;
if (ctx->kernel) {
- sr |= CXL_PSL_SR_An_R | (mfmsr() & MSR_SF);
- sr |= CXL_PSL_SR_An_HV;
+ if (!ctx->real_mode)
+ sr |= CXL_PSL_SR_An_R;
+ sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
} else {
sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
sr &= ~(CXL_PSL_SR_An_HV);