habanalabs: fix calculation of DRAM base address in PCIe BAR

The calculation of the device DRAM base address before setting the
relevant PCIe BAR to point at it, has an assumption that this BAR is
used to access only the DRAM, and thus the covered DRAM size is a power
of 2.
In future ASICs it is not necessarily true, so need to update the
calculation to support also a non-power-of-2 size.

Signed-off-by: Tomer Tayar <ttayar@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>

1 files changed, 5 insertions, 1 deletions

diff --git a/drivers/misc/habanalabs/common/device.c b/drivers/misc/habanalabs/common/device.c
index b662d40f18e8..0b3097802b00 100644
--- a/drivers/misc/habanalabs/common/device.c
+++ b/drivers/misc/habanalabs/common/device.c
@@ -42,7 +42,11 @@ static uint64_t hl_set_dram_bar(struct hl_device *hdev, u64 addr)
 	struct asic_fixed_properties *prop = &hdev->asic_prop;
 	u64 bar_base_addr;
 
-	bar_base_addr = addr & ~(prop->dram_pci_bar_size - 0x1ull);
+	if (is_power_of_2(prop->dram_pci_bar_size))
+		bar_base_addr = addr & ~(prop->dram_pci_bar_size - 0x1ull);
+	else
+		bar_base_addr = DIV_ROUND_DOWN_ULL(addr, prop->dram_pci_bar_size) *
+				prop->dram_pci_bar_size;
 
 	return hdev->asic_funcs->set_dram_bar_base(hdev, bar_base_addr);
 }