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| author |   Oded Gabbay <ogabbay@kernel.org> | 2020-12-05 22:55:09 +0200 |
|---|---|---|
| committer | Oded Gabbay <ogabbay@kernel.org> | 2020-12-28 08:47:38 +0200 |
| commit | 0024c094851f718ccb0b797255292bdce850a01f (patch) | |
| tree | 460d579994cf17fc3eed0d85834eadcc3dbc0258 /drivers/misc/habanalabs/include | |
| parent | habanalabs: Revise comment to align with mirror list name (diff) | |
| download | linux-dev-0024c094851f718ccb0b797255292bdce850a01f.tar.xz linux-dev-0024c094851f718ccb0b797255292bdce850a01f.zip | |
habanalabs/gaudi: disable CGM at HW initialization
In case the clock gating was enabled in preboot we need to disable it
at the H/W initialization stage before touching the MME/TPC registers.
Otherwise, the ASIC can get stuck. If the security is enabled in
the firmware level, the CGM is always disabled and the driver can't
enable it.
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/include')
| -rw-r--r-- | drivers/misc/habanalabs/include/common/hl_boot_if.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/common/hl_boot_if.h b/drivers/misc/habanalabs/include/common/hl_boot_if.h index 755c4800f002..7cb5f2d3e565 100644 --- a/drivers/misc/habanalabs/include/common/hl_boot_if.h +++ b/drivers/misc/habanalabs/include/common/hl_boot_if.h @@ -150,6 +150,10 @@ * CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled. * Initialized in: linux * + * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled. + * FW initialized Clock Gating. + * Initialized in: preboot + * * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. * This is a main indication that the * running FW populates the device status @@ -171,6 +175,7 @@ #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << 9) #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << 10) #define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << 11) +#define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << 13) #define CPU_BOOT_DEV_STS0_ENABLED (1 << 31) enum cpu_boot_status { |