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authorOded Gabbay <oded.gabbay@gmail.com>2019-02-28 10:46:13 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-02-28 13:04:59 +0100
commit1e7c1ec14b03fa80783a6263084b2525c57592a1 (patch)
treeadf8cbb14eda6a4f28f7a4f34da7123b74fcb09c /drivers/misc
parenthabanalabs: disable CPU access on timeouts (diff)
downloadlinux-dev-1e7c1ec14b03fa80783a6263084b2525c57592a1.tar.xz
linux-dev-1e7c1ec14b03fa80783a6263084b2525c57592a1.zip
habanalabs: fix mmu cache registers init
This patch fix an incorrect initialization of the MMU cache registers. The shift operation was done in the wrong direction. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/misc')
-rw-r--r--drivers/misc/habanalabs/goya/goya.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c
index 5780041abe32..5444cd0824b4 100644
--- a/drivers/misc/habanalabs/goya/goya.c
+++ b/drivers/misc/habanalabs/goya/goya.c
@@ -2675,8 +2675,9 @@ static int goya_mmu_init(struct hl_device *hdev)
goya->hw_cap_initialized |= HW_CAP_MMU;
/* init MMU cache manage page */
- WREG32(mmSTLB_CACHE_INV_BASE_39_8, MMU_CACHE_MNG_ADDR >> 8);
- WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR << 40);
+ WREG32(mmSTLB_CACHE_INV_BASE_39_8,
+ lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
+ WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
/* Remove follower feature due to performance bug */
WREG32_AND(mmSTLB_STLB_FEATURE_EN,