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| author |   Takeshi Saito <takeshi.saito.xv@renesas.com> | 2019-02-08 20:30:02 +0100 |
|---|---|---|
| committer |   Ulf Hansson <ulf.hansson@linaro.org> | 2019-02-25 14:45:59 +0100 |
| commit | f0c8234cb9230e3fc128ab4739f65e30bb00ceb5 (patch) | |
| tree | 9c9801ec451c6aaf7a2cff875530cf28e69d7f6b /drivers/mmc/host/renesas_sdhi_internal_dmac.c | |
| parent | mmc: mmci: Send a CMD12 to clear the DPSM at errors (diff) | |
| download | linux-dev-f0c8234cb9230e3fc128ab4739f65e30bb00ceb5.tar.xz linux-dev-f0c8234cb9230e3fc128ab4739f65e30bb00ceb5.zip | |
mmc: renesas_sdhi: Change HW adjustment register according to speed mode
SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF
according to the mode. If it is inappropriate, CRC error tends to occur.
This adds variable "tap_hs400" for HS400 mode and configures SCC_DT2FF
as needed.
Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>
[wsa: rebased to upstream and updated commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund@ragnatech.se>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/renesas_sdhi_internal_dmac.c')
| -rw-r--r-- | drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c index 92c9b15252da..9dfafa2a90a3 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -81,6 +81,7 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { { .clk_rate = 0, .tap = 0x00000300, + .tap_hs400 = 0x00000704, }, }; |