diff options
| author |   Ritesh Harjani <riteshh@codeaurora.org> | 2017-01-10 12:30:51 +0530 |
|---|---|---|
| committer |   Ulf Hansson <ulf.hansson@linaro.org> | 2017-02-13 13:20:31 +0100 |
| commit | d7507aa1b988efd788846d62021e581bfca31ace (patch) | |
| tree | 3a35e382f353baa826b43d8322e9be8578f8971e /drivers/mmc/host/sdhci-msm.c | |
| parent | mmc: sdhci: Clear SDHCI_HS400_TUNING flag after platform_execute_tuning (diff) | |
| download | linux-dev-d7507aa1b988efd788846d62021e581bfca31ace.tar.xz linux-dev-d7507aa1b988efd788846d62021e581bfca31ace.zip | |
mmc: sdhci-msm: Make HS400 tuning follow as per recommeneded HW sequence
During tuning execution for HS400 mode, HW sequence recommends
to select MCLK_SEL/2(0x3) in VENDOR_SPEC & sdhc msm clock at GCC
to be 400MHZ (nearest supported clk). Add this change in tuning
sequence during HS400 tuning.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Tested-by: Jeremy McNicoll <jeremymc@redhat.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci-msm.c')
| -rw-r--r-- | drivers/mmc/host/sdhci-msm.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 84d29dd2cc9e..fa9bce3167da 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -151,7 +151,8 @@ static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host, */ if (ios.timing == MMC_TIMING_UHS_DDR50 || ios.timing == MMC_TIMING_MMC_DDR52 || - ios.timing == MMC_TIMING_MMC_HS400) + ios.timing == MMC_TIMING_MMC_HS400 || + host->flags & SDHCI_HS400_TUNING) clock *= 2; return clock; } @@ -611,7 +612,8 @@ void sdhci_msm_hc_select_mode(struct sdhci_host *host) { struct mmc_ios ios = host->mmc->ios; - if (ios.timing == MMC_TIMING_MMC_HS400) + if (ios.timing == MMC_TIMING_MMC_HS400 || + host->flags & SDHCI_HS400_TUNING) msm_hc_select_hs400(host); else msm_hc_select_default(host); @@ -831,6 +833,16 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) ios.timing == MMC_TIMING_UHS_SDR104)) return 0; + /* + * For HS400 tuning in HS200 timing requires: + * - select MCLK/2 in VENDOR_SPEC + * - program MCLK to 400MHz (or nearest supported) in GCC + */ + if (host->flags & SDHCI_HS400_TUNING) { + sdhci_msm_hc_select_mode(host); + msm_set_clock_rate_for_bus_mode(host, ios.clock); + } + retry: /* First of all reset the tuning block */ rc = msm_init_cm_dll(host); |