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authorMaurice Petallo <mauricex.r.petallo@intel.com>2014-07-08 19:11:01 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2014-07-10 14:58:29 +0200
commitf25c33724d1512a72554c0ad4cb70b43ba15374e (patch)
tree05aef5afbddc4d01c5facc90246293864f44e4dc /drivers/mmc/host/sdhci-pci.c
parentmmc: sdhci: Preset value not supported in Baytrail eMMC (diff)
downloadlinux-dev-f25c33724d1512a72554c0ad4cb70b43ba15374e.tar.xz
linux-dev-f25c33724d1512a72554c0ad4cb70b43ba15374e.zip
mmc: sdhci: add DDR50 1.8V mode support for BayTrail eMMC Controller
This is to enable DDR50 bus speed mode with 1.8V signaling capability for BayTrail ACPI and PCI mode eMMC Controller. Signed-off-by: Maurice Petallo <mauricex.r.petallo@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci-pci.c')
-rw-r--r--drivers/mmc/host/sdhci-pci.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index dc336ee6751e..42f4633d0060 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -268,7 +268,7 @@ static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
{
slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
- MMC_CAP_HW_RESET;
+ MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR;
slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
slot->hw_reset = sdhci_pci_int_hw_reset;
return 0;