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author | Brian Norris <computersforpeace@gmail.com> | 2016-09-28 13:34:58 -0700 |
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committer | Brian Norris <computersforpeace@gmail.com> | 2016-10-03 09:51:35 -0700 |
commit | 1e2da4ad2e9b23556630bc774d3b1aaa61c0a69e (patch) | |
tree | c886868b46dac770418459eaaa0988504011f2e8 /drivers/mtd/nand/brcmnand/iproc_nand.c | |
parent | mtdpart: Propagate _get/put_device() (diff) | |
parent | mtd: nand: Provide nand_cleanup() function to free NAND related resources (diff) | |
download | linux-dev-1e2da4ad2e9b23556630bc774d3b1aaa61c0a69e.tar.xz linux-dev-1e2da4ad2e9b23556630bc774d3b1aaa61c0a69e.zip |
Merge tag 'for-4.9' of github.com:linux-nand/linux
"
Notable core changes:
- add the infrastructure to automate NAND timings configuration
- provide a generic DT property to maximize ECC strength
The rest is just a bunch of minor drivers and core fixes/cleanup
patches.
"
Also not noted: some refactoring in the core bad block table handling,
to help with improving some of the logic in error cases.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd/nand/brcmnand/iproc_nand.c')
-rw-r--r-- | drivers/mtd/nand/brcmnand/iproc_nand.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/mtd/nand/brcmnand/iproc_nand.c b/drivers/mtd/nand/brcmnand/iproc_nand.c index 585596c549b2..4c6ae113664d 100644 --- a/drivers/mtd/nand/brcmnand/iproc_nand.c +++ b/drivers/mtd/nand/brcmnand/iproc_nand.c @@ -74,7 +74,8 @@ static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en) spin_unlock_irqrestore(&priv->idm_lock, flags); } -static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare) +static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare, + bool is_param) { struct iproc_nand_soc *priv = container_of(soc, struct iproc_nand_soc, soc); @@ -86,10 +87,19 @@ static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare) val = brcmnand_readl(mmio); - if (prepare) - val |= IPROC_NAND_APB_LE_MODE; - else + /* + * In the case of BE or when dealing with NAND data, alway configure + * the APB bus to LE mode before accessing the FIFO and back to BE mode + * after the access is done + */ + if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) || !is_param) { + if (prepare) + val |= IPROC_NAND_APB_LE_MODE; + else + val &= ~IPROC_NAND_APB_LE_MODE; + } else { /* when in LE accessing the parameter page, keep APB in BE */ val &= ~IPROC_NAND_APB_LE_MODE; + } brcmnand_writel(val, mmio); |