diff options
| author |   Vladimir Zapolskiy <vz@mleia.com> | 2015-10-01 02:23:37 +0300 |
|---|---|---|
| committer |   Brian Norris <computersforpeace@gmail.com> | 2015-10-04 22:30:49 +0100 |
| commit | d54e88011d0a5fb48d9bb60fede3e83375c75841 (patch) | |
| tree | 8c349483fdc14ac36a5d7967097c6aaf400f1bba /drivers/mtd/nand/lpc32xx_slc.c | |
| parent | mtd: nand: lpc32xx_slc: fix potential overflow over 4 bits (diff) | |
| download | linux-dev-d54e88011d0a5fb48d9bb60fede3e83375c75841.tar.xz linux-dev-d54e88011d0a5fb48d9bb60fede3e83375c75841.zip | |
mtd: nand: lpc32xx_slc: fix calculation of timing arcs from given values
According to LPC32xx User's Manual all values measured in clock cycles
are programmable from 1 to 16 clocks (4 bits) starting from 0 in
bitfield, the current version of calculated clock cycles is too
conservative.
Correctness of 0 bitfield value (i.e. programmed 1 clock
timing) is proven with actual NAND chip devices.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd/nand/lpc32xx_slc.c')
| -rw-r--r-- | drivers/mtd/nand/lpc32xx_slc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index a9e8a02cdac5..cbf4501090b8 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -95,7 +95,7 @@ * slc_tac register definitions **********************************************************************/ /* Computation of clock cycles on basis of controller and device clock rates */ -#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, 1 + (c / n), 0xF) << s) +#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s) /* Clock setting for RDY write sample wait time in 2*n clocks */ #define SLCTAC_WDR(n) (((n) & 0xF) << 28) |