diff options
| author |   Miquel Raynal <miquel.raynal@bootlin.com> | 2021-05-27 10:49:58 +0200 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2021-06-18 09:45:20 +0200 |
| commit | 23739c34f56c7eaa62d00b70dc8bf31b8244ef83 (patch) | |
| tree | fcebab391aeb2c0ab62126c98e5cb35d0dbf2008 /drivers/mtd/nand/raw/arasan-nand-controller.c | |
| parent | mtd: rawnand: onfi: Fix endianness when reading NV-DDR values (diff) | |
| download | linux-dev-23739c34f56c7eaa62d00b70dc8bf31b8244ef83.tar.xz linux-dev-23739c34f56c7eaa62d00b70dc8bf31b8244ef83.zip | |
mtd: rawnand: arasan: Rename the data interface register
There are 2 timing registers:
- "data interface"
- "timings"
So far, the "data interface" register was named "timings" which begins
misleading when bringing support for the "timings" register. Rename it
to "data_iface".
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210527084959.208804-1-miquel.raynal@bootlin.com
Diffstat (limited to 'drivers/mtd/nand/raw/arasan-nand-controller.c')
| -rw-r--r-- | drivers/mtd/nand/raw/arasan-nand-controller.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index f9b5b140720b..5bcc680984f0 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -144,7 +144,7 @@ struct anfc_op { * @rb: Ready-busy line * @page_sz: Register value of the page_sz field to use * @clk: Expected clock frequency to use - * @timings: Data interface timing mode to use + * @data_iface: Data interface timing mode to use * @ecc_conf: Hardware ECC configuration value * @strength: Register value of the ECC strength * @raddr_cycles: Row address cycle information @@ -164,7 +164,7 @@ struct anand { unsigned int rb; unsigned int page_sz; unsigned long clk; - u32 timings; + u32 data_iface; u32 ecc_conf; u32 strength; u16 raddr_cycles; @@ -331,7 +331,7 @@ static int anfc_select_target(struct nand_chip *chip, int target) anfc_assert_cs(nfc, nfc_cs_idx); /* Update the controller timings and the potential ECC configuration */ - writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG); + writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG); /* Update clock frequency */ if (nfc->cur_clk != anand->clk) { @@ -970,11 +970,11 @@ static int anfc_setup_interface(struct nand_chip *chip, int target, return 0; if (nand_interface_is_sdr(conf)) - anand->timings = DIFACE_SDR | - DIFACE_SDR_MODE(conf->timings.mode); + anand->data_iface = DIFACE_SDR | + DIFACE_SDR_MODE(conf->timings.mode); else - anand->timings = DIFACE_NVDDR | - DIFACE_DDR_MODE(conf->timings.mode); + anand->data_iface = DIFACE_NVDDR | + DIFACE_DDR_MODE(conf->timings.mode); anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; |