diff options
| author |   Cédric Le Goater <clg@kaod.org> | 2017-08-02 10:51:51 +0200 |
|---|---|---|
| committer |   Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> | 2017-08-14 17:23:50 +0200 |
| commit | 811cb897564625f196258f15bab485b9bbdd7a36 (patch) | |
| tree | 17dff0dbc048d061d9a1a44abcddb8cc1a93b5bd /drivers/mtd/spi-nor/aspeed-smc.c | |
| parent | mtd: mtk-quadspi: Remove unneeded pinctrl header (diff) | |
| download | linux-dev-811cb897564625f196258f15bab485b9bbdd7a36.tar.xz linux-dev-811cb897564625f196258f15bab485b9bbdd7a36.zip | |
mtd: spi-nor: aspeed: set 4B setting for all chips
The driver made the wrong assumption that the 4B setting was
autodetected for all chips of the AST2500 FMC flash controller. This
is only the case for the CS0.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Diffstat (limited to 'drivers/mtd/spi-nor/aspeed-smc.c')
| -rw-r--r-- | drivers/mtd/spi-nor/aspeed-smc.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index 0106357421bd..8d3cbe27efb6 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -621,19 +621,18 @@ static void aspeed_smc_chip_set_type(struct aspeed_smc_chip *chip, int type) } /* - * The AST2500 FMC flash controller should be strapped by hardware, or - * autodetected, but the AST2500 SPI flash needs to be set. + * The first chip of the AST2500 FMC flash controller is strapped by + * hardware, or autodetected, but other chips need to be set. Enforce + * the 4B setting for all chips. */ static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip) { struct aspeed_smc_controller *controller = chip->controller; u32 reg; - if (chip->controller->info == &spi_2500_info) { - reg = readl(controller->regs + CE_CONTROL_REG); - reg |= 1 << chip->cs; - writel(reg, controller->regs + CE_CONTROL_REG); - } + reg = readl(controller->regs + CE_CONTROL_REG); + reg |= 1 << chip->cs; + writel(reg, controller->regs + CE_CONTROL_REG); } /* |