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| author |   Michael Walle <michael@walle.cc> | 2020-01-16 10:37:00 +0100 |
|---|---|---|
| committer |   Miquel Raynal <miquel.raynal@bootlin.com> | 2020-01-17 22:45:05 +0100 |
| commit | da2ef8124f20b4ce18d1d3d24fc7b88e687e10bb (patch) | |
| tree | a436e99d9d264150d2d64a170d2653aa23c4211f /drivers/mtd | |
| parent | mtd: spi-nor: Fix selection of 4-byte addressing opcodes on Spansion (diff) | |
| download | linux-dev-da2ef8124f20b4ce18d1d3d24fc7b88e687e10bb.tar.xz linux-dev-da2ef8124f20b4ce18d1d3d24fc7b88e687e10bb.zip | |
mtd: spi-nor: Fix quad enable for Spansion like flashes
The commit 7b678c69c0ca ("mtd: spi-nor: Merge spansion Quad Enable
methods") forgot to actually set the QE bit in some cases. Thus this
breaks quad mode accesses to flashes which support readback of the
status register-2. Fix it.
Fixes: 7b678c69c0ca ("mtd: spi-nor: Merge spansion Quad Enable methods")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 97f68d70cd23..b0cd443dd758 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2124,6 +2124,8 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) return 0; + nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; + return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); } |