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| author |   Eilon Greenstein <eilong@broadcom.com> | 2009-02-12 08:38:32 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2009-02-15 23:31:58 -0800 |
| commit | 356e23850b5ed4471470a918623021765fcaf125 (patch) | |
| tree | 35de737e86c377773db50abf4a90a631541eb601 /drivers/net/bnx2x_fw_defs.h | |
| parent | bnx2x: Comments and prints (diff) | |
| download | linux-dev-356e23850b5ed4471470a918623021765fcaf125.tar.xz linux-dev-356e23850b5ed4471470a918623021765fcaf125.zip | |
bnx2x: Clean-up
Whitespaces, empty lines, 80 columns, indentations and removing redundant
parenthesis
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_fw_defs.h')
| -rw-r--r-- | drivers/net/bnx2x_fw_defs.h | 54 |
1 files changed, 25 insertions, 29 deletions
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h index 0683e542e942..05d695dea61c 100644 --- a/drivers/net/bnx2x_fw_defs.h +++ b/drivers/net/bnx2x_fw_defs.h @@ -217,14 +217,13 @@ #define X_ETH_LOCAL_RING_SIZE 13 #define FIRST_BD_IN_PKT 0 #define PARSE_BD_INDEX 1 -#define NUM_OF_ETH_BDS_IN_PAGE \ - ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8)) +#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) /* Rx ring params */ -#define U_ETH_LOCAL_BD_RING_SIZE (16) -#define U_ETH_LOCAL_SGE_RING_SIZE (12) -#define U_ETH_SGL_SIZE (8) +#define U_ETH_LOCAL_BD_RING_SIZE 16 +#define U_ETH_LOCAL_SGE_RING_SIZE 12 +#define U_ETH_SGL_SIZE 8 #define U_ETH_BDS_PER_PAGE_MASK \ @@ -246,15 +245,15 @@ #define U_ETH_UNDEFINED_Q 0xFF /* values of command IDs in the ramrod message */ -#define RAMROD_CMD_ID_ETH_PORT_SETUP (80) -#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85) -#define RAMROD_CMD_ID_ETH_STAT_QUERY (90) -#define RAMROD_CMD_ID_ETH_UPDATE (100) -#define RAMROD_CMD_ID_ETH_HALT (105) -#define RAMROD_CMD_ID_ETH_SET_MAC (110) -#define RAMROD_CMD_ID_ETH_CFC_DEL (115) -#define RAMROD_CMD_ID_ETH_PORT_DEL (120) -#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125) +#define RAMROD_CMD_ID_ETH_PORT_SETUP 80 +#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85 +#define RAMROD_CMD_ID_ETH_STAT_QUERY 90 +#define RAMROD_CMD_ID_ETH_UPDATE 100 +#define RAMROD_CMD_ID_ETH_HALT 105 +#define RAMROD_CMD_ID_ETH_SET_MAC 110 +#define RAMROD_CMD_ID_ETH_CFC_DEL 115 +#define RAMROD_CMD_ID_ETH_PORT_DEL 120 +#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125 /* command values for set mac command */ @@ -271,8 +270,8 @@ #define ETH_MAX_RX_CLIENTS_E1H 25 /* Maximal aggregation queues supported */ -#define ETH_MAX_AGGREGATION_QUEUES_E1 (32) -#define ETH_MAX_AGGREGATION_QUEUES_E1H (64) +#define ETH_MAX_AGGREGATION_QUEUES_E1 32 +#define ETH_MAX_AGGREGATION_QUEUES_E1H 64 /* ETH RSS modes */ #define ETH_RSS_MODE_DISABLED 0 @@ -301,7 +300,7 @@ #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) /* microcode fixed page page size 4K (chains and ring segments) */ -#define MC_PAGE_SIZE (4096) +#define MC_PAGE_SIZE 4096 /* Host coalescing constants */ @@ -348,16 +347,16 @@ #define ATTENTION_ID 4 /* max number of slow path commands per port */ -#define MAX_RAMRODS_PER_PORT (8) +#define MAX_RAMRODS_PER_PORT 8 /* values for RX ETH CQE type field */ -#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0) -#define RX_ETH_CQE_TYPE_ETH_RAMROD (1) +#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0 +#define RX_ETH_CQE_TYPE_ETH_RAMROD 1 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ -#define EMULATION_FREQUENCY_FACTOR (1600) -#define FPGA_FREQUENCY_FACTOR (100) +#define EMULATION_FREQUENCY_FACTOR 1600 +#define FPGA_FREQUENCY_FACTOR 100 #define TIMERS_TICK_SIZE_CHIP (1e-3) #define TIMERS_TICK_SIZE_EMUL \ @@ -371,12 +370,9 @@ #define TSEMI_CLK1_RESUL_FPGA \ ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) -#define USEMI_CLK1_RESUL_CHIP \ - (TIMERS_TICK_SIZE_CHIP) -#define USEMI_CLK1_RESUL_EMUL \ - (TIMERS_TICK_SIZE_EMUL) -#define USEMI_CLK1_RESUL_FPGA \ - (TIMERS_TICK_SIZE_FPGA) +#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP) +#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL) +#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA) #define XSEMI_CLK1_RESUL_CHIP (1e-3) #define XSEMI_CLK1_RESUL_EMUL \ @@ -401,7 +397,7 @@ #define XSTORM_IP_ID_ROLL_HALF 0x8000 #define XSTORM_IP_ID_ROLL_ALL 0 -#define FW_LOG_LIST_SIZE (50) +#define FW_LOG_LIST_SIZE 50 #define NUM_OF_PROTOCOLS 4 #define NUM_OF_SAFC_BITS 16 |