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| author |   Dong Aisheng <aisheng.dong@nxp.com> | 2018-12-13 07:08:00 +0000 |
|---|---|---|
| committer |   Marc Kleine-Budde <mkl@pengutronix.de> | 2019-07-24 10:31:55 +0200 |
| commit | 8c306bec2d09c8436eea989b1be2a381cae93418 (patch) | |
| tree | ba985d49c5bd51db29eb86923934eac84904701e /drivers/net/can/flexcan.c | |
| parent | dt-bindings: can: flexcan: add PE clock source property to device tree (diff) | |
| download | linux-dev-8c306bec2d09c8436eea989b1be2a381cae93418.tar.xz linux-dev-8c306bec2d09c8436eea989b1be2a381cae93418.zip | |
can: flexcan: add support for PE clock source select
Add support to select the clock source for CAN Protocol Engine (PE).
It's SoC Implementation dependent. Refer to RM for detailed definition
of each SoC. We select clock source 1 (peripheral clock) by default in
driver now, this patch adds support to parse the clock source from the DT.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'drivers/net/can/flexcan.c')
| -rw-r--r-- | drivers/net/can/flexcan.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index 228ac5d1f3b4..bcc39512f342 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -275,6 +275,8 @@ struct flexcan_priv { u8 tx_mb_idx; u8 mb_count; u8 mb_size; + u8 clk_src; /* clock source of CAN Protocol Engine */ + u32 reg_ctrl_default; u32 reg_imask1_default; u32 reg_imask2_default; @@ -1369,7 +1371,10 @@ static int register_flexcandev(struct net_device *dev) goto out_clks_disable; reg = priv->read(®s->ctrl); - reg |= FLEXCAN_CTRL_CLK_SRC; + if (priv->clk_src) + reg |= FLEXCAN_CTRL_CLK_SRC; + else + reg &= ~FLEXCAN_CTRL_CLK_SRC; priv->write(reg, ®s->ctrl); err = flexcan_chip_enable(priv); @@ -1501,6 +1506,7 @@ static int flexcan_probe(struct platform_device *pdev) struct clk *clk_ipg = NULL, *clk_per = NULL; struct flexcan_regs __iomem *regs; int err, irq; + u8 clk_src = 1; u32 clock_freq = 0; reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); @@ -1509,9 +1515,12 @@ static int flexcan_probe(struct platform_device *pdev) else if (IS_ERR(reg_xceiver)) reg_xceiver = NULL; - if (pdev->dev.of_node) + if (pdev->dev.of_node) { of_property_read_u32(pdev->dev.of_node, "clock-frequency", &clock_freq); + of_property_read_u8(pdev->dev.of_node, + "fsl,clk-source", &clk_src); + } if (!clock_freq) { clk_ipg = devm_clk_get(&pdev->dev, "ipg"); @@ -1580,6 +1589,7 @@ static int flexcan_probe(struct platform_device *pdev) priv->regs = regs; priv->clk_ipg = clk_ipg; priv->clk_per = clk_per; + priv->clk_src = clk_src; priv->devtype_data = devtype_data; priv->reg_xceiver = reg_xceiver; |