diff options
| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-07-10 12:52:45 +0100 |
|---|---|---|
| committer |   Marc Kleine-Budde <mkl@pengutronix.de> | 2022-07-19 20:46:59 +0200 |
| commit | 2d99bfbf3386962692dcccd73931cb0db07a1a43 (patch) | |
| tree | 5a1d57beda78b2dac5c4926e710b7312ec99fb4b /drivers/net/can/sja1000/sja1000.c | |
| parent | dt-bindings: can: nxp,sja1000: Document RZ/N1{D,S} support (diff) | |
| download | linux-dev-2d99bfbf3386962692dcccd73931cb0db07a1a43.tar.xz linux-dev-2d99bfbf3386962692dcccd73931cb0db07a1a43.zip | |
can: sja1000: Add Quirk for RZ/N1 SJA1000 CAN controller
As per Chapter 6.5.16 of the RZ/N1 Peripheral Manual, The SJA1000
CAN controller does not support Clock Divider Register compared to
the reference Philips SJA1000 device.
This patch adds a device quirk to handle this difference.
Link: https://lore.kernel.org/all/20220710115248.190280-4-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'drivers/net/can/sja1000/sja1000.c')
| -rw-r--r-- | drivers/net/can/sja1000/sja1000.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/net/can/sja1000/sja1000.c b/drivers/net/can/sja1000/sja1000.c index 2e7638f98cf1..d9da471f1bb9 100644 --- a/drivers/net/can/sja1000/sja1000.c +++ b/drivers/net/can/sja1000/sja1000.c @@ -183,8 +183,9 @@ static void chipset_init(struct net_device *dev) { struct sja1000_priv *priv = netdev_priv(dev); - /* set clock divider and output control register */ - priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN); + if (!(priv->flags & SJA1000_QUIRK_NO_CDR_REG)) + /* set clock divider and output control register */ + priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN); /* set acceptance filter (accept all) */ priv->write_reg(priv, SJA1000_ACCC0, 0x00); @@ -209,7 +210,8 @@ static void sja1000_start(struct net_device *dev) set_reset_mode(dev); /* Initialize chip if uninitialized at this stage */ - if (!(priv->read_reg(priv, SJA1000_CDR) & CDR_PELICAN)) + if (!(priv->flags & SJA1000_QUIRK_NO_CDR_REG || + priv->read_reg(priv, SJA1000_CDR) & CDR_PELICAN)) chipset_init(dev); /* Clear error counters and error code capture */ |