diff options
| author |   Vivien Didelot <vivien.didelot@savoirfairelinux.com> | 2017-06-08 18:34:12 -0400 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2017-06-09 12:10:59 -0400 |
| commit | 0898432cc296cc27cee6647f6748f2add37e09b6 (patch) | |
| tree | 3f96064c1f71b9fd0b0e93f77eecd024a4c243ec /drivers/net/dsa/mv88e6xxx/port.c | |
| parent | net: dsa: mv88e6xxx: do not prefix ops with g1 (diff) | |
| download | linux-dev-0898432cc296cc27cee6647f6748f2add37e09b6.tar.xz linux-dev-0898432cc296cc27cee6647f6748f2add37e09b6.zip | |
net: dsa: mv88e6xxx: rework pause limit operation
All Marvell chips supporting Pause frames limiting use 1-byte value for
input and output.
Old chips have both bytes adjacent in a 16-bit register. New ones have
an indirect table using 8-bit data.
The mv88e6xxx library functions (such as in port.c) must not contain
driver logic, but only generic helpers. This patch changes the
port_pause_config operation for port_pause_limit taking two u8 arguments
for input and output limits. There is no functional changes.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/mv88e6xxx/port.c')
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx/port.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index 46e73ca0ac4d..ee94d16789a2 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -376,22 +376,24 @@ int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) * the remote end or the period of time that this port can pause the * remote end. */ -int mv88e6097_port_pause_config(struct mv88e6xxx_chip *chip, int port) +int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, + u8 out) { - return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000); + return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, out << 8 | in); } -int mv88e6390_port_pause_config(struct mv88e6xxx_chip *chip, int port) +int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, + u8 out) { int err; err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, - PORT_FLOW_CTRL_LIMIT_IN | 0); + PORT_FLOW_CTRL_LIMIT_IN | in); if (err) return err; return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, - PORT_FLOW_CTRL_LIMIT_OUT | 0); + PORT_FLOW_CTRL_LIMIT_OUT | out); } /* Offset 0x04: Port Control Register */ |