diff options
| author |   Vladimir Oltean <olteanv@gmail.com> | 2019-10-16 21:41:02 +0300 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2019-10-18 12:55:30 -0400 |
| commit | 2fb079a28ae856145e8977d08b77403a3a5d6a70 (patch) | |
| tree | e5b7f51f2a6b207f6d2f4355e35c6b7b7e78ae4b /drivers/net/dsa/sja1105/sja1105.h | |
| parent | net: netsec: Correct dma sync for XDP_TX frames (diff) | |
| download | linux-dev-2fb079a28ae856145e8977d08b77403a3a5d6a70.tar.xz linux-dev-2fb079a28ae856145e8977d08b77403a3a5d6a70.zip | |
net: dsa: sja1105: Switch to hardware operations for PTP
Adjusting the hardware clock (PTPCLKVAL, PTPCLKADD, PTPCLKRATE) is a
requirement for the auxiliary PTP functionality of the switch
(TTEthernet, PPS input, PPS output).
Therefore we need to switch to using these registers to keep a
synchronized time in hardware, instead of the timecounter/cyclecounter
implementation, which is reliant on the free-running PTPTSCLK.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/sja1105/sja1105.h')
| -rw-r--r-- | drivers/net/dsa/sja1105/sja1105.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/net/dsa/sja1105/sja1105.h b/drivers/net/dsa/sja1105/sja1105.h index 0ef97a916707..397a49da35e4 100644 --- a/drivers/net/dsa/sja1105/sja1105.h +++ b/drivers/net/dsa/sja1105/sja1105.h @@ -33,9 +33,8 @@ struct sja1105_regs { u64 config; u64 rmii_pll1; u64 ptp_control; - u64 ptpclk; + u64 ptpclkval; u64 ptpclkrate; - u64 ptptsclk; u64 ptpegr_ts[SJA1105_NUM_PORTS]; u64 pad_mii_tx[SJA1105_NUM_PORTS]; u64 pad_mii_id[SJA1105_NUM_PORTS]; |