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| author |   Vladimir Oltean <vladimir.oltean@nxp.com> | 2021-05-31 01:59:36 +0300 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2021-05-31 22:40:26 -0700 |
| commit | 91a050782cbfc8f81c7c6aa0c5ce396bea51df3b (patch) | |
| tree | 047358fd244090ea8f57ce462b721732fdf040f0 /drivers/net/dsa/sja1105/sja1105.h | |
| parent | net: dsa: sja1105: cache the phy-mode port property (diff) | |
| download | linux-dev-91a050782cbfc8f81c7c6aa0c5ce396bea51df3b.tar.xz linux-dev-91a050782cbfc8f81c7c6aa0c5ce396bea51df3b.zip | |
net: dsa: sja1105: add a PHY interface type compatibility matrix
On the SJA1105, all ports support the parallel "xMII" protocols (MII,
RMII, RGMII) except for port 4 on SJA1105R/S which supports only SGMII.
This was relatively easy to model, by special-casing the SGMII port.
On the SJA1110, certain ports can be pinmuxed between SGMII and xMII, or
between SGMII and an internal 100base-TX PHY. This creates problems,
because the driver's assumption so far was that if a port supports
SGMII, it uses SGMII.
We allow the device tree to tell us how the port pinmuxing is done, and
check that against a PHY interface type compatibility matrix for
plausibility.
The other big change is that instead of doing SGMII configuration based
on what the port supports, we do it based on what is the configured
phy_mode of the port.
The 2500base-x support added in this patch is not complete.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/dsa/sja1105/sja1105.h')
| -rw-r--r-- | drivers/net/dsa/sja1105/sja1105.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/dsa/sja1105/sja1105.h b/drivers/net/dsa/sja1105/sja1105.h index d5c0217b1f65..a27841642693 100644 --- a/drivers/net/dsa/sja1105/sja1105.h +++ b/drivers/net/dsa/sja1105/sja1105.h @@ -111,6 +111,11 @@ struct sja1105_info { enum packing_op op); int (*clocking_setup)(struct sja1105_private *priv); const char *name; + bool supports_mii[SJA1105_MAX_NUM_PORTS]; + bool supports_rmii[SJA1105_MAX_NUM_PORTS]; + bool supports_rgmii[SJA1105_MAX_NUM_PORTS]; + bool supports_sgmii[SJA1105_MAX_NUM_PORTS]; + bool supports_2500basex[SJA1105_MAX_NUM_PORTS]; }; enum sja1105_key_type { |