diff options
| author |   Andrew Lunn <andrew@lunn.ch> | 2015-11-20 03:56:24 +0100 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2015-11-23 11:53:10 -0500 |
| commit | c8c1b39a86940edd35439f1e5c9ff39888daf0f0 (patch) | |
| tree | b315bb7d08318d8cf53b1a22ad5505d1840706f4 /drivers/net/dsa | |
| parent | net: dsa: Add support for a switch reset gpio (diff) | |
| download | linux-dev-c8c1b39a86940edd35439f1e5c9ff39888daf0f0.tar.xz linux-dev-c8c1b39a86940edd35439f1e5c9ff39888daf0f0.zip | |
dsa: mv88e6xxx.c: Hardware reset the chip if available
The device tree binding now allows a gpio to be specified which is
attached to the switch chips reset line. If it is defined, perform
a hardware reset on the switch during setup.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa')
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c index b06dba05594a..75e245c4235e 100644 --- a/drivers/net/dsa/mv88e6xxx.c +++ b/drivers/net/dsa/mv88e6xxx.c @@ -19,6 +19,7 @@ #include <linux/list.h> #include <linux/module.h> #include <linux/netdevice.h> +#include <linux/gpio/consumer.h> #include <linux/phy.h> #include <net/dsa.h> #include <net/switchdev.h> @@ -2323,6 +2324,7 @@ int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) { struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); u16 is_reset = (ppu_active ? 0x8800 : 0xc800); + struct gpio_desc *gpiod = ds->pd->reset; unsigned long timeout; int ret; int i; @@ -2336,6 +2338,14 @@ int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) /* Wait for transmit queues to drain. */ usleep_range(2000, 4000); + /* If there is a gpio connected to the reset pin, toggle it */ + if (gpiod) { + gpiod_set_value_cansleep(gpiod, 1); + usleep_range(10000, 20000); + gpiod_set_value_cansleep(gpiod, 0); + usleep_range(10000, 20000); + } + /* Reset the switch. Keep the PPU active if requested. The PPU * needs to be active to support indirect phy register access * through global registers 0x18 and 0x19. |