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authorLendacky, Thomas <Thomas.Lendacky@amd.com>2017-06-28 13:43:18 -0500
committerDavid S. Miller <davem@davemloft.net>2017-06-29 15:14:19 -0400
commit7e1e6b86a5d96ca13834fbc6b6e54a9228f308e1 (patch)
treec53ead63dc615f9f12b00300ae3a12c871b31dc6 /drivers/net/ethernet/amd/xgbe/xgbe-main.c
parentamd-xgbe: Prepare for more fine grained cache coherency controls (diff)
downloadlinux-dev-7e1e6b86a5d96ca13834fbc6b6e54a9228f308e1.tar.xz
linux-dev-7e1e6b86a5d96ca13834fbc6b6e54a9228f308e1.zip
amd-xgbe: Simplify the burst length settings
Currently the driver hardcodes the PBLx8 setting. Remove the need for specifying the PBLx8 setting and automatically calculate based on the specified PBL value. Since the PBLx8 setting applies to both Tx and Rx use the same PBL value for both of them. Also, the driver currently uses a bit field to set the AXI master burst len setting. Change to the full bit field range and set the burst length based on the specified value. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/amd/xgbe/xgbe-main.c')
-rw-r--r--drivers/net/ethernet/amd/xgbe/xgbe-main.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
index 982368b560ba..8eec9f5991f5 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
@@ -140,14 +140,13 @@ static void xgbe_default_config(struct xgbe_prv_data *pdata)
{
DBGPR("-->xgbe_default_config\n");
- pdata->pblx8 = DMA_PBL_X8_ENABLE;
+ pdata->blen = DMA_SBMR_BLEN_256;
+ pdata->pbl = DMA_PBL_128;
pdata->tx_sf_mode = MTL_TSF_ENABLE;
pdata->tx_threshold = MTL_TX_THRESHOLD_64;
- pdata->tx_pbl = DMA_PBL_16;
pdata->tx_osp_mode = DMA_OSP_ENABLE;
pdata->rx_sf_mode = MTL_RSF_DISABLE;
pdata->rx_threshold = MTL_RX_THRESHOLD_64;
- pdata->rx_pbl = DMA_PBL_16;
pdata->pause_autoneg = 1;
pdata->tx_pause = 1;
pdata->rx_pause = 1;