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authorLendacky, Thomas <Thomas.Lendacky@amd.com>2016-11-03 13:17:48 -0500
committerDavid S. Miller <davem@davemloft.net>2016-11-04 14:48:43 -0400
commit586e3cfb260a0c6026321417bb5af331cc717f40 (patch)
tree683071ac468f143e6bbcf3f5f2ec5bc44066e0b4 /drivers/net/ethernet/amd/xgbe/xgbe.h
parentamd-xgbe: Fix formatting of PCS register dump (diff)
downloadlinux-dev-586e3cfb260a0c6026321417bb5af331cc717f40.tar.xz
linux-dev-586e3cfb260a0c6026321417bb5af331cc717f40.zip
amd-xgbe: Prepare for priority-based FIFO allocation
Currently, the Rx and Tx fifos are evenly allocated between the hardware queues of the device. As more queues are instantiated, the fifo memory needs to be able to be allocated based on queue priority. This allows for higher priority queues to have more fifo memory than lower priority queues. Prepare for this by modifying the current fifo calculation to assign the fifo queue allocation in an array that is then used to program the hardware. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/amd/xgbe/xgbe.h')
-rw-r--r--drivers/net/ethernet/amd/xgbe/xgbe.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 5dd17dcea2f8..d838b44a9952 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -208,7 +208,8 @@
#define XGMAC_DRIVER_CONTEXT 1
#define XGMAC_IOCTL_CONTEXT 2
-#define XGBE_FIFO_MAX 81920
+#define XGMAC_FIFO_RX_MAX 81920
+#define XGMAC_FIFO_TX_MAX 81920
#define XGBE_TC_MIN_QUANTUM 10