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author | Mark Starovoytov <mstarovoitov@marvell.com> | 2020-05-22 11:19:43 +0300 |
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committer | David S. Miller <davem@davemloft.net> | 2020-05-22 14:08:28 -0700 |
commit | 7327699f35f8e90b32c03080b5cba4e9aa95e087 (patch) | |
tree | 8e18469819df2e1181a574e9593c086980a26330 /drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h | |
parent | net: atlantic: make TCVEC2RING accept nic_cfg (diff) | |
download | linux-dev-7327699f35f8e90b32c03080b5cba4e9aa95e087.tar.xz linux-dev-7327699f35f8e90b32c03080b5cba4e9aa95e087.zip |
net: atlantic: QoS implementation: max_rate
This patch adds initial support for mqprio rate limiters (max_rate only).
Atlantic HW supports Rate-Shaping for time-sensitive traffic at per
Traffic Class (TC) granularity.
Target rate is defined by:
* nominal link rate (always 10G);
* rate factor (ratio between nominal rate and max allowed).
Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h')
-rw-r--r-- | drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h index 5d86ffab4ece..06220792daf1 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h @@ -2056,6 +2056,24 @@ /* default value of bitfield tx_tc_mode */ #define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 +/* tx tx_desc_rate_mode bitfield definitions + * preprocessor definitions for the bitfield "tx_desc_rate_mode". + * port="pif_tps_desc_rate_mode_i" + */ + +/* register address for bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_ADR 0x00007900 +/* bitmask for bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSK 0x00000080 +/* inverted bitmask for bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSKN 0xFFFFFF7F +/* lower bit position of bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT 7 +/* width of bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_WIDTH 1 +/* default value of bitfield tx_desc_rate_mode */ +#define HW_ATL_TPS_TX_DESC_RATE_MODE_DEFAULT 0x0 + /* tx tx_buf_en bitfield definitions * preprocessor definitions for the bitfield "tx_buf_en". * port="pif_tpb_tx_buf_en_i" @@ -2275,6 +2293,58 @@ /* default value of bitfield data_tc_arb_mode */ #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 +/* tx desc{r}_rate_en bitfield definitions + * preprocessor definitions for the bitfield "desc{r}_rate_en". + * port="pif_tps_desc_rate_en_i[0]" + */ + +/* register address for bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_ADR(desc) (0x00007408 + (desc) * 0x10) +/* bitmask for bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_MSK 0x80000000 +/* inverted bitmask for bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_MSKN 0x7FFFFFFF +/* lower bit position of bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_SHIFT 31 +/* width of bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_WIDTH 1 +/* default value of bitfield desc{r}_rate_en */ +#define HW_ATL_TPS_DESC_RATE_EN_DEFAULT 0x0 + +/* tx desc{r}_rate_x bitfield definitions + * preprocessor definitions for the bitfield "desc{r}_rate_x". + * port="pif_tps_desc0_rate_x" + */ +/* register address for bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_ADR(desc) (0x00007408 + (desc) * 0x10) +/* bitmask for bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_MSK 0x03FF0000 +/* inverted bitmask for bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_MSKN 0xFC00FFFF +/* lower bit position of bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_SHIFT 16 +/* width of bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_WIDTH 10 +/* default value of bitfield desc{r}_rate_x */ +#define HW_ATL_TPS_DESC_RATE_X_DEFAULT 0x0 + +/* tx desc{r}_rate_y bitfield definitions + * preprocessor definitions for the bitfield "desc{r}_rate_y". + * port="pif_tps_desc0_rate_y" + */ +/* register address for bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_ADR(desc) (0x00007408 + (desc) * 0x10) +/* bitmask for bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_MSK 0x00003FFF +/* inverted bitmask for bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_MSKN 0xFFFFC000 +/* lower bit position of bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_SHIFT 0 +/* width of bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_WIDTH 14 +/* default value of bitfield desc{r}_rate_y */ +#define HW_ATL_TPS_DESC_RATE_Y_DEFAULT 0x0 + /* tx desc_rate_ta_rst bitfield definitions * preprocessor definitions for the bitfield "desc_rate_ta_rst". * port="pif_tps_desc_rate_ta_rst_i" |