diff options
| author |   Matt Carlson <mcarlson@broadcom.com> | 2011-11-21 15:01:18 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2011-11-22 16:01:34 -0500 |
| commit | 513aa6ea39adfc9daf5b4bc33b49008733c3eb51 (patch) | |
| tree | 3b4850d1b93f7e88ed0c9972c36c2e228fb6a3a5 /drivers/net/ethernet/broadcom | |
| parent | tg3: Make 1000Base-X FC resolution look like 1000T (diff) | |
| download | linux-dev-513aa6ea39adfc9daf5b4bc33b49008733c3eb51.tar.xz linux-dev-513aa6ea39adfc9daf5b4bc33b49008733c3eb51.zip | |
tg3: Adjust BD replenish thresholds
The BD replenish thresholds for the 57765 and newer ASIC revs are a
little strict. They were tuned for a mode that is currently unused.
This patch relaxes the thresholds so that they are set to values more
inline with the resources available.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom')
| -rw-r--r-- | drivers/net/ethernet/broadcom/tg3.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 2497cc4ca89d..09d2003f56fc 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -8171,7 +8171,8 @@ static void tg3_setup_rxbd_thresholds(struct tg3 *tp) if (!tg3_flag(tp, 5750_PLUS) || tg3_flag(tp, 5780_CLASS) || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || + tg3_flag(tp, 57765_PLUS)) bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) @@ -8191,10 +8192,7 @@ static void tg3_setup_rxbd_thresholds(struct tg3 *tp) if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) return; - if (!tg3_flag(tp, 5705_PLUS)) - bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; - else - bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; + bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); |