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| author |   Salil <salil.mehta@huawei.com> | 2017-08-02 16:59:49 +0100 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2017-08-03 15:08:17 -0700 |
| commit | 848440544b41fbe21f36072ee7dc7c3c59ce62e2 (patch) | |
| tree | 4413b1ce8170feb2a7d0569c6cafee7b68af7b41 /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c | |
| parent | net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support (diff) | |
| download | linux-dev-848440544b41fbe21f36072ee7dc7c3c59ce62e2.tar.xz linux-dev-848440544b41fbe21f36072ee7dc7c3c59ce62e2.zip | |
net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver
THis patch adds the support of the Scheduling and Shaping
functionalities during the transmit leg. This also adds the
support of Pause at MAC level. (Pause at per-priority level
shall be added later along with the DCB feature).
Hardware as such consists of two types of cofiguration of 6 level
schedulers. Algorithms varies according to the level and type
of scheduler being used. Current patch is used to initialize
the mapping, algorithms(like SP, DWRR etc) and shaper(CIR, PIR etc)
being used.
Signed-off-by: Daode Huang <huangdaode@hisilicon.com>
Signed-off-by: lipeng <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c')
0 files changed, 0 insertions, 0 deletions