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| author |   Bruce Allan <bruce.w.allan@intel.com> | 2013-01-12 07:26:53 +0000 |
|---|---|---|
| committer |   Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2013-01-28 00:12:03 -0800 |
| commit | 39149d4da6d50de92f9e7f70c743a8b8c20eeac1 (patch) | |
| tree | ee6697659236fa4c071f29940d0fcfc8e0261bd6 /drivers/net/ethernet/intel/e1000e/defines.h | |
| parent | e1000e: cleanup hw.h (diff) | |
| download | linux-dev-39149d4da6d50de92f9e7f70c743a8b8c20eeac1.tar.xz linux-dev-39149d4da6d50de92f9e7f70c743a8b8c20eeac1.zip | |
e1000e: cleanup: remove comments which are no longer applicable
Code was removed but the applicable comments were not.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/e1000e/defines.h')
| -rw-r--r-- | drivers/net/ethernet/intel/e1000e/defines.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h index c4587671dc73..d29b2fd4c09c 100644 --- a/drivers/net/ethernet/intel/e1000e/defines.h +++ b/drivers/net/ethernet/intel/e1000e/defines.h @@ -261,8 +261,6 @@ #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ -/* Constants used to interpret the masked PCI-X bus speed. */ - #define HALF_DUPLEX 1 #define FULL_DUPLEX 2 @@ -330,8 +328,6 @@ #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ -/* Transmit Arbitration Count */ - /* SerDes Control */ #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 @@ -800,9 +796,6 @@ #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* Auto crossover enabled all speeds */ #define M88E1000_PSCR_AUTO_X_MODE 0x0060 -/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) - * 0=Normal 10BASE-T Rx Threshold - */ #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ /* M88E1000 PHY Specific Status Register */ |