diff options
| author |   Matt Jared <matthew.a.jared@intel.com> | 2014-04-23 04:50:03 +0000 |
|---|---|---|
| committer |   Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2014-06-06 01:59:58 -0700 |
| commit | 351499ab2e3f7020ee9a4fbdacaed644984ad359 (patch) | |
| tree | 39ec77ecc6300f8cd58df777d96acfe1da8b8aaa /drivers/net/ethernet/intel/i40evf/i40e_register.h | |
| parent | i40e/i40evf: check AQ register for valid data (diff) | |
| download | linux-dev-351499ab2e3f7020ee9a4fbdacaed644984ad359.tar.xz linux-dev-351499ab2e3f7020ee9a4fbdacaed644984ad359.zip | |
i40e/i40evf: add Tx pre queue disable function
Add a function which indicates our intention to enable or disable a particular
Tx queue. Also add a function to notify the device's Tx unit that we're about
to enable or disable a Tx queue.
Change-ID: I6adf3cbb5bb3e3c984d1ec969e06577c19ef296d
Signed-off-by: Matt Jared <matthew.a.jared@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Tested-by: Jim Young <jamesx.m.young@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/i40evf/i40e_register.h')
| -rw-r--r-- | drivers/net/ethernet/intel/i40evf/i40e_register.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_register.h b/drivers/net/ethernet/intel/i40evf/i40e_register.h index 7977205b1e04..369839655818 100644 --- a/drivers/net/ethernet/intel/i40evf/i40e_register.h +++ b/drivers/net/ethernet/intel/i40evf/i40e_register.h @@ -1585,6 +1585,14 @@ #define I40E_GLLAN_TSOMSK_M 0x000442DC #define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0 #define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK (0xFFF << I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT) +#define I40E_GLLAN_TXPRE_QDIS(_i) (0x000E6500 + ((_i) * 4)) /* i=0..11 */ +#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 +#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK (0x7FF << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) +#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 +#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK (0x1 << I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) +#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 +#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK (0x1 << I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) + #define I40E_PFLAN_QALLOC 0x001C0400 #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 #define I40E_PFLAN_QALLOC_FIRSTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) |