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| author |   Olof Johansson <olof@lixom.net> | 2019-05-15 22:51:48 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2019-05-15 22:51:48 -0700 |
| commit | 7a0c4c17089a8aff52f516f0f52002be52950aae (patch) | |
| tree | 474dc451d62a1ba788ed52c4cecf93f9e50cc39a /drivers/net/ethernet/intel/igb/e1000_defines.h | |
| parent | Merge tag 'v5.2-rockchip-soc32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/soc (diff) | |
| parent | Merge tag 'davinci-fixes-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into fixes (diff) | |
| download | linux-dev-7a0c4c17089a8aff52f516f0f52002be52950aae.tar.xz linux-dev-7a0c4c17089a8aff52f516f0f52002be52950aae.zip | |
Merge branch 'fixes' into arm/soc
Merge in a few pending fixes from pre-5.1 that didn't get sent in:
MAINTAINERS: update arch/arm/mach-davinci
ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnect
ARM: dts: imx6q-logicpd: Reduce inrush current on USBH1
ARM: dts: imx6q-logicpd: Reduce inrush current on start
ARM: dts: imx: Fix the AR803X phy-mode
ARM: dts: sun8i: a33: Reintroduce default pinctrl muxing
arm64: dts: allwinner: a64: Rename hpvcc-supply to cpvdd-supply
ARM: sunxi: fix a leaked reference by adding missing of_node_put
ARM: sunxi: fix a leaked reference by adding missing of_node_put
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/net/ethernet/intel/igb/e1000_defines.h')
| -rw-r--r-- | drivers/net/ethernet/intel/igb/e1000_defines.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h index 01fcfc6f3415..d2e2c50ce257 100644 --- a/drivers/net/ethernet/intel/igb/e1000_defines.h +++ b/drivers/net/ethernet/intel/igb/e1000_defines.h @@ -194,6 +194,8 @@ /* enable link status from external LINK_0 and LINK_1 pins */ #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ +#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ #define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ #define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ #define E1000_CTRL_RST 0x04000000 /* Global reset */ |